6.2 Shift Registers and Data Storage Elements

6.2 Shift Registers and Data Storage Elements

Appendix I 5.5(a) is level 2 for B1 and B2/B2L; shift registers are taught here as an exam-useful sequential application beyond a single bistable, not as a separately printed current syllabus bullet. Once a D flip-flop can capture one bit (section 6.1), a row of those cells sharing a clock becomes a shift register or a storage register. Category B2/B2L candidates also need the diagram-reading skill in 5.5(b) (section 6.3) to recognise the same blocks on an aircraft logic drawing. Module 5 timing is unchanged: about 75 seconds per question, 75% pass, no essay.

A shift register is a cascade of edge-triggered D flip-flops. The serial input (SI) drives D of stage 0. Q of stage 0 drives D of stage 1, Q of stage 1 drives D of stage 2, and so on. All CLK pins are common. On each capturing edge every bit moves one place toward the serial output (SO = Q of the last stage). After n clocks, a bit that entered SI appears at SO of an n-stage device. Between edges the pattern is stored — that is the memory. If the serial path is ignored and each D is fed from a parallel pin, the same hardware is a storage register (PIPO hold).

Four organisations: SISO, SIPO, PISO, PIPO

The four names describe where data enters and where it leaves. They are the same D-cell chain with different pins bonded out.

SISO. Only SI and SO are used. The register is an n-clock delay. A 1 that enters SI of a four-bit SISO appears at SO four edges later. Intermediate Q pins may exist on the IC but are not the intended interface. SISO is the least common aircraft discrete interface because the technician cannot see the word until it has fully walked out.

SIPO. Bits enter SI, one per clock. After n edges the n bits sit on Q0…Q(n−1) at once. That is serial loading of a discrete word: a remote concentrator or a maintenance computer sends eight discretes down one pair, bit 0 first (or bit 7 first — the drawing states the order), and the SIPO presents eight parallel Q pins to warning captions, relay drivers or a computer input port. Until the nth clock, the Q pins still hold the previous word, which is why a 'load complete' or frame-strobe discrete often qualifies the parallel outputs.

PISO. A load (or parallel-enable) pulse writes P0…P(n−1) into the D cells in one clock. Subsequent clocks with load deasserted shift that word out of SO, one bit per edge. The aircraft use is the complement of SIPO: many discretes at a wing or landing-gear interface must travel to a computer on one serial line. Load samples the pack; shift serialises it.

PIPO. Parallel pins in, parallel pins out. With shift-enable false the device is a storage register: clocks either do nothing (hold) or reload from the P pins, depending on the load pin. With shift-enable true it behaves as a shifter and the parallel outputs show the walking pattern. Universal shift-register ICs combine all four modes behind a two-bit mode select.

Hold versus shift

Each stage needs a small multiplexer in front of D:

• Shift: D of stage k takes Q of stage k−1 (stage 0 takes SI).
• Hold: D of stage k takes its own Q, so the next clock rewrites the same bit — the pattern does not walk. Some designs simply gate the clock instead of recirculating; the effect is the same: clocks do not move data.
• Parallel load: D of stage k takes pin Pk, usually for one clock only.

A deasserted shift-enable therefore means hold: the stored discrete word stays put even though the system clock keeps running. Asserted shift-enable means the word walks. Confusing hold with reset is a common error — hold keeps the bits; a clear/reset pin forces them to 0.

Worked four-bit SIPO load. SI sequence on successive clocks is 1, 0, 1, 1 (bit 0 first). Start from 0000:

• Clock 1: Q = 1000 if Q0 is the SI end, or 0001 if Q3 is the SI end — read the drawing.
• Clock 2: the 1 moves one stage and the new 0 enters.
• Clock 3: pattern 101x (order depends on which end is SI).
• Clock 4: the word 1011 is present on the four Q pins.

If the same chain is in hold during those clocks, Q remains 0000 and the SI bits are ignored. That is why a serial discrete frame is qualified by a shift-enable that is high only for the n clocks of the word, then low so the parallel Q pins freeze for the rest of the frame.

Serial loading of discrete words on the aircraft

A typical landing-gear interface pack might contain eight discretes: left and right down-and-locked, left and right up-and-locked, doors closed, weight-on-wheels, and two spares. Running eight separate wires through a pressurised bulkhead is heavy. The pack is sampled in parallel at the gear bay (PISO), sent as a serial frame on one screened pair, and recovered by a SIPO on the warning or landing-gear control card. The technician tracing a 'gear not down' caption that is stuck must ask: is the bit wrong at the parallel pack, in the serial bitstream (wrong clock, wrong enable, dropped bit), or at the SIPO Q pin? A logic diagram that shows only the SIPO will not reveal a PISO fault in the bay — 5.5(a) is the application; 5.5(b) is reading that split across two drawings.

Clock polarity still matters. A rising-edge SIPO ignores SI except at the rising edge. If SI is a slow open-collector discrete that has not reached a valid 1 before setup time, that bit is captured as 0 for the whole word. Serial loading therefore still depends on the setup/hold rules of section 6.1.

Ring and Johnson counters — brief context

If the last Q is wired back to SI, the register is a ring counter. Loading a single 1 and then shifting produces a one-hot pattern that repeats every n clocks (n distinct states for n stages). If NOT of the last Q is wired back to SI, the register is a Johnson (twisted-ring) counter with 2n distinct states for n stages (a four-stage Johnson counts 8 states: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, then repeats). Both are sequential applications of a shift register. They appear as timing sequencers and as some lamp-test or stepper patterns. They are not the usual path for loading an arbitrary discrete word: a ring that started with 0000 stays 0000 forever, so a discrete pack of mixed 1s and 0s would be lost. For mixed words use SIPO/PISO; treat ring/Johnson as circulating-shift special cases when the feedback wire is visible on the diagram.

Reading the storage element on a schematic

Identify the block by pins, not by the word 'register' in a note:

1. Common CLK triangle → sequential, edge-triggered.
2. One SI and several Q pins, no P pins → SIPO.
3. Several P pins, one SO, a LOAD pin → PISO.
4. Mode or SH/LD pin → hold versus shift versus load.
5. Feedback from last Q (or NOT Q) to SI → ring or Johnson, not a data-word register.

A bank of D cells with only D and Q and a shared clock, no serial cascade, is a parallel storage register (PIPO hold). That is the memory-bit row of section 6.1 drawn as one symbol. Do not call it a shift register unless a serial path is actually wired.