5.3 Universal Gates and Aircraft Combinational Applications

5.3 Universal Gates and Aircraft Combinational Applications

The former detailed Appendix I description for 5.5(a) paired identification with applications used for aircraft systems and schematic diagrams; the current consolidated text uses the shorter “Identification and applications” wording. The networks in this section remain combinational: the output at any instant depends only on the present inputs. Discrete interlocks, gear-down-and-locked coincidence, and warning-lamp summation are AND and OR functions, often built from NAND or NOR packages because those two gates are universal.

A gate family is universal if, using only members of that family, you can realise NOT, AND and OR. Any Boolean expression then follows by substitution. NAND is universal. NOR is universal. AND alone is not (it cannot invert). OR alone is not. XOR alone is not. OpenExamPrep treats these constructions as independent Module 5 study; they are not an EASA-approved wiring standard for a named aeroplane type.

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NAND as a universal gate

NOT from NAND. Tie both inputs of a two-input NAND together, or drive both pins from the same net. The truth table collapses: input 0 gives NAND(0,0) = 1; input 1 gives NAND(1,1) = 0. That is inversion. An equivalent shop practice on a multi-input NAND is to tie unused inputs HIGH and use one remaining input as the signal; NAND with one input HIGH is an inverter on the other input, because 1 · A is A and the NAND then complements it. Do not leave a CMOS input open: a float is not a defined 1. Do not tie both inputs permanently to 0 V and expect inversion — the output then sits stuck HIGH.

AND from NAND. AND is NAND followed by inversion. Two NAND packages: the first computes (A·B)′; the second, wired as a NOT, complements that result back to A·B. On a schematic this often appears as two NAND symbols in series, the second with its inputs joined. It is still combinational AND, not a latch.

OR from NAND. De Morgan: A + B = (A′ · B′)′. Invert each input with a NAND-wired NOT, then NAND those inverted signals together. The final NAND is the OR. In distinctive-shape language this is the NAND equivalent of OR with inverted inputs, which Section 5.2 already identified as the dual of NAND.

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NOR as a universal gate

NOT from NOR. Tie both inputs together: NOR(0,0) = 1, NOR(1,1) = 0. Unused NOR inputs are tied LOW so they do not force the output to 0.

OR from NOR. OR is NOR followed by inversion: two NOR packages, the second used as NOT.

AND from NOR. De Morgan: A · B = (A′ + B′)′. Invert each input with a NOR-wired NOT, then NOR those inverted signals. That NOR of inverted inputs is AND.

Avionics discrete cards often stock one universal type in quantity (commonly NAND in TTL-era teaching, sometimes NOR in CMOS packs) so that every combinational function on the board uses the same package. Mixed AND, OR and NOT symbols on a functional schematic may therefore appear as walls of NAND on the circuit schematic. They are equivalent if De Morgan and the extra inverters are drawn correctly.

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Discrete interlock

An interlock is a combinational enable: an actuator, valve, starter or test function is allowed only when every safety condition is present and no inhibit is present. In Boolean form:

Y = (condition1) · (condition2) · … · (inhibit)′

That is AND of the required discretes, with active-low inhibits inverted so that a true inhibit forces Y to 0. Examples used in training include: enable a hydraulic pump only when fire-handle not pulled AND oil pressure sane; enable a thrust-reverser test only when weight-on-wheels AND reverse not already unlocked. The maintenance point is the coincidence: one false required input, or one asserted inhibit, must drop Y. That is AND behaviour, not OR.

If the inhibit arrives already active-low (bar over the name), the AND input that receives it may be drawn without an extra inverter — the active-low pin is the inversion. Adding a second inverter by mistake would AND with the released inhibit and defeat the interlock. Read the bar before you add a bubble.

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Landing gear down-and-locked: AND

A green gear-down indication that is allowed only when every leg is down and locked is the textbook aircraft AND:

Y_green = (nose down-and-locked) · (left main down-and-locked) · (right main down-and-locked)

Three proximity or landing-gear-control-unit discretes. Y is 1 only for the single combination in which all three asserted-true inputs are 1. Any one unlocked leg forces Y to 0, which is the fail-safe sense for a “all down and locked” lamp. XOR would light green when an odd number of legs reported locked — useless as an interlock. Inclusive OR would light green if a single leg locked — unsafe as an “all locked” caption. NOR would light when all three reports were 0 (all unlocked).

Active-low proximity switches. Many installations pull a discrete LOW when the target is near (locked). The asserted-true down-and-locked state is then 0 on the wire. The coincidence of three asserted-low signals is electrically NOR of the raw lines (output HIGH only when every raw line is LOW), or AND after each line is inverted. Those two drawings are De Morgan equivalents. On the schematic, look for bubbles on the AND inputs or a NOR symbol feeding the green lamp driver. Do not “correct” NOR to AND without moving the inversions; you would invert the meaning of locked.

A red gear-unsafe or disagreement lamp is a different function: it is often driven when the handle and the proximity set do not match, which is closer to XOR or to an OR of disagreement bits. This chapter’s required identification is the down-and-locked AND (or its NOR equivalent with active-low inputs), not the sequential gear-position sequencer.

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Warning lamp: OR of faults

A master caution or a shared warning lamp that must illuminate if any one of several independent fault discretes is true is inclusive OR:

Y_lamp = F1 + F2 + F3 + … + Fn

The lamp is 0 only when every fault input is 0. AND would require every fault to be present at once before the crew saw a light. XNOR would light when faults matched, including the all-healthy case if that pattern were “all zeros matching”. A binary counter that tallies faults over time is sequential and is not the 5.5(a) combinational lamp.

Active-low fault discretes (open-collector, asserted LOW) are often wired-OR on a single pull-up: any transistor pulling the node LOW asserts the bus. That wired node is electrically equivalent to AND of active-high “healthy” lines, or to OR of active-low “fault” lines — another De Morgan pair. The functional schematic still shows OR of faults feeding the caution driver.

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Schematic reading recipe

1. Name each net as asserted-high or asserted-low from the bar or bubble.
2. Identify the IEC mark or distinctive shape, then apply bubbles: & with output circle is NAND; ≥1 with output circle is NOR; & with input circles is NOR.
3. If the card is all NAND or all NOR, rebuild AND and OR with the universal constructions above. NAND then NAND-as-NOT is AND. That pair driving a lamp is the landing-gear coincidence, not an exclusive-OR and not a toggle flip-flop.
4. Translate back to the aircraft sentence: all conditions → AND; any condition → OR; not → inversion on that pin only.
5. Confirm combinational behaviour: changing an input now must be able to change the output now, with no clock edge required.

Worked schematic. Two down-and-locked discretes A and B, active-high, feed a NAND whose output goes to a second NAND used as an inverter, and that inverter drives a green LED. First NAND produces (A·B)′. Second NAND as NOT produces ((A·B)′)′ = A·B. The lamp is AND. Replacing the second NAND with a direct connection would leave the lamp driven by NAND, so the LED would be dark only when both legs were locked — the opposite of the required indication.

Level 2 means you can walk that chain on a wiring diagram, state the Boolean function at the lamp, and choose AND for all-locked coincidence and OR for any-fault warning without reaching for sequential symbols.