5.1 Basic Logic Gates, Truth Tables and Logic Levels

5.1 Basic Logic Gates, Truth Tables and Logic Levels

Commission Implementing Regulation (EU) 2023/989 sets Appendix I topic 5.5(a), Identification and applications, at level 2 for B1 and B2/B2L. The common gate symbols, truth tables, equivalent circuits, aircraft applications, and schematics used here come from the pre-12 June 2024 detailed description and established logic-circuit teaching, not from detail printed in current Appendix I. Knowledge is level 2 for both category B1 and category B2/B2L. Categories A and B3 are not examined on 5.5. Module 5 is a multiple-choice paper only: B2 sits 72 questions in 90 minutes, B1 sits 40 questions in 50 minutes, with a 75% pass mark, no negative marking, and no essay. The live paper uses three options; the practice items in this chapter use four. OpenExamPrep publishes this material as independent exam preparation; it is not an EASA document and does not claim official approval or partnership.

A combinational logic circuit produces outputs that depend only on the present combination of inputs. There is no stored memory of earlier values. Sequential devices such as flip-flops, latches and counters hold history and are treated in a later chapter. If a symbol shows a clock pin or a feedback path that retains a previous state, it is not a combinational gate of the type identified in 5.5(a).

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Logic levels and families

Digital gates treat voltage as two states. In the positive logic used throughout this module, 1 = HIGH = TRUE and 0 = LOW = FALSE. Two families appear constantly on training cards and in aircraft discrete logic.

TTL (transistor–transistor logic) on the classic 74-series uses a 5 V supply (VCC). Standard teaching thresholds that technicians still meet on interface cards are:

• Output HIGH minimum VOH ≈ 2.4 V; output LOW maximum VOL ≈ 0.4 V
• Input HIGH minimum VIH = 2.0 V; input LOW maximum VIL = 0.8 V
• DC noise margin ≈ 0.4 V on both sides (VOH − VIH and VIL − VOL)

A TTL HIGH is not required to be 5 V. A legal HIGH may sit near 2.4 V. A probe reading of 2.2 V on a TTL input is in the undefined band, not a guaranteed 1. Do not call that line high enough merely because it is nearer 5 V than 0 V.

CMOS (complementary metal-oxide-semiconductor) families such as 74HC typically accept about 2 V to 6 V; 5 V and 3.3 V rails are the usual teaching values in avionics. Outputs swing close to the rails (near 0 V and near VDD). For many HC parts, VIL ≈ 0.3 × VDD and VIH ≈ 0.7 × VDD. 74HCT is CMOS with TTL-compatible input thresholds (VIL 0.8 V, VIH 2.0 V) so mixed 5 V families can share a discrete bus. CMOS inputs take negligible DC current. A floating CMOS input can pick up electromagnetic interference and chatter, so unused inputs are tied HIGH or LOW — never left open.

Do not judge a 3.3 V CMOS HIGH against a 5 V TTL VOH figure copied from a different card. The family drawn on that schematic sets the legal voltage window.

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Active-high and active-low

Active-high means the named condition is true when the line is HIGH. Active-low means the named condition is true when the line is LOW. Drawings show active-low with a bar over the signal name or a small inversion circle (bubble) on the pin. A weight-on-wheels discrete labelled active-low is asserted at LOW, not when the wire sits at 5 V. The gate still obeys its truth table; the aircraft meaning of true is the asserted polarity. Mixing electrical HIGH with asserted TRUE is a standard 5.5(a) trap on landing-gear and caution discretes.

Positive logic is the default: 1 = HIGH. Negative logic (1 assigned to LOW) appears in some older textbooks; if a question does not mention it, treat 1 as HIGH.

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Truth tables and 2^n combinations

For n independent binary inputs a complete truth table has 2^n rows. Two inputs give four rows (00, 01, 10, 11). Three inputs give eight. Four inputs give sixteen. Listing only the interesting rows is not a complete table and will miss a fail-safe combination on an interlock.

Boolean product (·) is AND; Boolean sum (+) is inclusive OR — not arithmetic plus. In Boolean algebra, 1 + 1 = 1.

NOT (inverter). One input. Y is the complement of A. IEC uses a rectangle marked 1 with a circle on the output. A buffer is the same rectangle marked 1 without a circle (Y = A). The circle is the inversion; omitting it is a different function.

AND. Y is 1 only if all inputs are 1. A three-input AND is 1 only for the single row 111. That is why all-landing-gear-down-and-locked indications are AND functions: one 0 (one leg not locked) forces the output to 0.

OR. Y is 1 if any input is 1. The only two-input 0 output is row 00. Master caution and any-door-open lamps are OR functions.

NAND. Complement of AND. Output is 0 only when every input is 1; every other row is 1. Two-input NAND of 11 is 0; of 00, 01 and 10 is 1.

NOR. Complement of OR. Output is 1 only when every input is 0. Two-input NOR of 00 is 1; any 1 input forces 0.

XOR (exclusive-OR). For two inputs, Y is 1 when the inputs differ (01 and 10). Rows 00 and 11 give 0. For more than two inputs the usual definition is odd parity: Y is 1 when an odd number of inputs are 1. XOR is not inclusive OR: inclusive OR is also 1 for 11. Comparators and parity-check teaching circuits use XOR.

XNOR (exclusive-NOR, equivalence). Complement of XOR. Two-input XNOR is 1 when the inputs match (00 or 11). Equality detectors and even-parity checks use XNOR.

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Symbols and equivalent circuits on schematics

Appendix I 5.5(a) expects identification. Two drawing languages appear in training manuals and OEM wiring diagrams.

Distinctive-shape (ANSI/IEEE 91) symbols: AND looks like a D, OR like a shield, XOR like OR with a second curved input line. Inversion is a bubble on the affected pin.

IEC 60617 rectangular symbols: every gate is a rectangle. The function is the qualifying symbol inside the box: & for AND, ≥1 for OR, 1 for buffer or inverter, =1 for XOR. Inversion is still a circle on the pin, not a change of the internal mark. & with an output circle is NAND, not AND. ≥1 with an output circle is NOR, not OR. =1 plus an output circle is XNOR.

A circle on an input inverts that input before the function; a circle on the output inverts the result. Equivalent circuits in the next section rest on that rule.

Switch and diode equivalent circuits remain combinational and help you recognise the same functions in discrete hardware:

• AND equivalent: series switches — the path is closed only if every switch is closed. Positive-logic diode AND: cathodes to the inputs, anodes common at the output, pull-up to VCC; any LOW input pulls Y LOW.
• OR equivalent: parallel switches — the path is closed if any switch is closed. Positive-logic diode OR: anodes to the inputs, cathodes common at the output, pull-down to 0 V; any HIGH input pulls Y HIGH.
• NOT equivalent: a single inverting transistor stage (HIGH in produces LOW out).

NAND and NOR are those AND or OR cores plus an inversion. They are electrically equivalent to AND-plus-inverter and OR-plus-inverter.

Multi-input gates keep the same definitions. Unused AND or NAND inputs are tied HIGH so they do not force a 0; unused OR or NOR inputs are tied LOW so they do not force a 1. CMOS unused pins must not float. Open-collector or open-drain discrete drivers often sit LOW when asserted and are pulled HIGH by a resistor when released. That is an active-low interface, not an error in the AND or OR symbol upstream.

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Exam reading order

With about 75 seconds per question, use a fixed recipe: identify the symbol (distinctive shape or IEC mark, then bubbles); write the 2^n input rows; fill Y from the definition (AND = all, OR = any, XOR = differ or odd, then complement for NAND, NOR and XNOR); if names are active-low, translate each pin so asserted = 1, apply the table, then translate the output polarity back to the lamp or coil.

Keep the identification facts mechanical: seven functions, 2^n rows, TTL 2.0 V / 0.8 V input thresholds on 5 V 74-series, CMOS near-rail outputs and tied unused pins, and active-low asserted at LOW. Those facts are the 5.5(a) core before Boolean simplification.