6.1 Bistable Multivibrators: SR, JK, D and T Flip-Flops

6.1 Bistable Multivibrators: SR, JK, D and T Flip-Flops

Commission Implementing Regulation (EU) 2023/989 sets Appendix I topic 5.5(a), Identification and applications, at knowledge level 2 for both category B1 and category B2/B2L. Categories A and B3 are not examined on 5.5. Sequential applications — devices that store a bit — are taught here as a practical expansion of that broad heading. Interpretation of complete logic diagrams is a separate head, 5.5(b), examined at level 2 for B2/B2L only; B1 is not required to interpret diagrams at that depth. Module 5 is a multiple-choice paper: B2 sits 72 questions in 90 minutes, B1 sits 40 questions in 50 minutes, A/B3 sit 20 questions in 25 minutes, with a 75% pass mark, no negative marking, and no essay. The live paper uses three options; the practice items in this chapter use four options.

Combinational gates (AND, OR, NAND, NOR, XOR) produce an output that is a function of the present inputs only. Sequential logic adds memory: the output depends on the present inputs and on a stored previous state. That memory cell is the bistable multivibrator. A bistable has two stable states, conventionally Q = 1 (set) and Q = 0 (reset). The complementary pin, written NOT Q or Q-bar, is the inverse of Q when the cell is healthy. Two families appear on aircraft digital cards: the latch, which is level-sensitive, and the edge-triggered flip-flop, which updates only on a specified clock transition.

Latch versus edge-triggered flip-flop

A latch remains transparent while its enable (or gated clock) sits at the active level: Q can follow the data pins for the whole of that interval. When enable returns inactive, the last value is held. An edge-triggered flip-flop samples its controlling pins only at a rising or falling clock edge, then ignores those pins until the next edge. Aircraft sequential designs almost always distribute a common square-wave clock so that a bank of bits updates together. Treating a transparent latch as if it were edge-triggered is a standard maintenance error: a bouncing discrete on a still-enabled latch chatters Q, whereas the same bounce arriving between clock edges of a flip-flop is ignored.

The clock pin on a flip-flop symbol carries a triangle. No inversion bubble on that triangle means a rising-edge trigger; a bubble means a falling-edge trigger. A latch symbol uses an enable labelled EN or G and has no edge triangle. Asynchronous preset (PR) and clear (CLR) pins, often active-low (drawn with bubbles), override the clocked path and force Q immediately. Setup time is the interval for which data must be stable before the capturing edge; hold time is the interval it must remain stable after the edge. Violating either can leave the cell metastable — Q hovers between 0 and 1 before collapsing at random — which on the aircraft looks like an intermittent latched discrete that sometimes stores the new value and sometimes does not.

SR latch: Set, Reset and the forbidden state

The SR (Set–Reset) latch is the elementary bistable. Cross-coupled NOR gates give an active-high SR; cross-coupled NAND gates give an active-low S-bar / R-bar latch. For the NOR (active-high) version the four input rows are:

When S = 1 and R = 1, the latch is in the forbidden (invalid) state. Releasing both inputs back to 0 then starts a race: whichever gate is slightly faster wins, so the next stored bit is unpredictable. Exam items often present S = R = 1 and ask why a designer must prevent it. On an aircraft schematic the usual preventives are mechanically exclusive contacts (a break-before-make SPDT switch cannot close Set and Reset together) or a combinational interlock in front of S and R.

A clocked (gated) SR latch ANDs S and R with an enable so that the pins are ignored unless the clock level is active. The forbidden combination still exists while the latch is enabled. Tying R to NOT D converts the gated SR into a D latch and deletes the forbidden row, because a single data pin cannot demand Set and Reset at once.

For the NAND active-low latch the hold combination is S-bar = R-bar = 1 (both pins released high) and the forbidden combination is S-bar = R-bar = 0 (both pins pulled low). Read the bubbles on the drawing: active-low Set is asserted by a 0, not by a 1.

JK flip-flop: J = K = 1 is toggle, not forbidden

The JK flip-flop keeps the SR idea but redefines the both-asserted combination as toggle. J behaves like Set, K like Reset, and a clock edge is required.

When J = 1 and K = 1, Q flips on every capturing edge. That is defined behaviour — it is not the SR forbidden row. The characteristic equation is next-Q = (J AND NOT Q) OR (NOT K AND Q). A JK with J and K strapped together is a T flip-flop; a JK held with J = K = 1 on every clock is a divide-by-two stage.

If a JK were merely a level-sensitive latch, holding J = K = 1 for the whole clock pulse would let Q toggle at gate-delay rate (the 1s-catching race). Master–slave JK cells and modern edge-triggered JK cells sample J and K only at the edge, so one clock produces one toggle. On a schematic, look for the edge triangle before predicting toggle.

Aircraft use of JK includes a memory bit with separate Set (J) and Reset (K) from two system computers, a binary divider when J = K = 1, and the first stage of a synchronous counter (section 6.3).

D flip-flop: capture of one data bit

The D (data, sometimes called delay) flip-flop has one data pin D and a clock. On the capturing edge, Q becomes equal to D. Between edges Q holds. The characteristic is simply next-Q = D. There is no forbidden data combination through D. Many packaged D cells still expose asynchronous PR and CLR; those pins must sit inactive (usually high if they are active-low) unless a power-up reset is required.

A register is a row of D flip-flops sharing a clock. Capturing a discrete on a defined edge is why D cells appear on aircraft input cards: a squat-switch, a thrust-lever idle discrete, or a fire-handle microswitch is filtered and then sampled so that contact bounce between clocks never reaches the warning computer. Q is then a clean memory bit for the rest of the frame.

T flip-flop: dedicated toggle

The T (toggle) flip-flop has input T and a clock. T = 0 holds; T = 1 toggles Q on the edge. Frequency at Q is half the clock frequency while T remains 1, which is why T stages form binary counters and 1 Hz elapsed-time ticks from a faster crystal. A T cell is a JK with J = K = T, or a D cell with D wired to NOT Q when T is 1.

Aircraft applications: debounce and memory bits

Two 5.5(a) sequential applications dominate Module 5 teaching.

Contact debounce. A mechanical toggle or limit switch does not close cleanly. Over a few milliseconds the contacts bounce, producing a burst of edges. If that raw discrete clocks a counter or a warning computer, one throw is counted many times. An SR latch driven by two break-before-make contacts (one Set, one Reset) captures a single transition and holds it until the opposite contact asserts Reset. An alternative is an RC filter into a Schmitt trigger feeding a D flip-flop that samples after the bounce window. The stored Q is the debounced discrete.

Memory bits (latched discretes). Fire warnings, many latched cautions, and BITE fault-captured bits must remain asserted after the initiating spike has gone. A 20 ms overcurrent that only drove a combinational AND would light a caption for 20 ms and then go dark — useless to the crew. An SR or D cell Sets on the event and holds Q = 1 until a guarded Reset, a valid 'condition gone AND reset selected' AND-gate, or a flight-leg power cycle. When a schematic shows a rectangle with Q and a clock triangle, treat it as a memory bit. When it shows cross-coupled NAND or NOR, treat it as an SR latch and look for the interlock that prevents S = R = 1.