7.1 Computer Architecture, Terminology and the Bus System

7.1 Computer Architecture, Terminology and the Bus System

Appendix I of Commission Implementing Regulation (EU) 2023/989, topic 5.6(a), requires terminology and computer technology in aircraft systems at knowledge level 2 for categories B1 and B2/B2L and level 1 for categories A and B3. Topic 5.6(b), Computer operation, is level 2 for B2/B2L only; the microcomputer layout and address, data, and control-bus detail used here comes from the former detailed Appendix I description; B1, A and B3 are not examined on 5.6(b). This section therefore teaches the shared 5.6(a) vocabulary in enough depth for B1 and B2, then develops the B2 board-level architecture that 5.6(b) names. Microprocessor fetch–execute timing, registers and the ALU belong to topic 5.7 (section 7.3). Semiconductor memory families in depth belong to section 7.2.

Module 5 is a multiple-choice paper only. Category B2/B2L sits 72 questions in 90 minutes, B1 sits 40 in 50 minutes, and A/B3 sit 20 in 25 minutes, with a 75% pass mark, no negative marking, and no essay. The live paper uses three options; the practice items here use four. Fees are set by the national aviation authority or the approved Part-147 organisation; EASA does not publish a single official euro fee. Examination credit remains valid for 10 years preceding licence application. OpenExamPrep publishes this material as independent exam preparation; it is not an EASA document and does not claim official approval or partnership.

Bits, bytes and word length

A bit (binary digit) is the smallest unit of digital information. It has two states, conventionally 0 and 1, which map onto two electrical levels (for example 0 V and +5 V TTL, or 0 V and +3.3 V CMOS). Every address, instruction, discrete and serial data field on the aircraft is a pattern of bits.

A byte is a group of eight bits. One byte can represent 2^8 = 256 distinct patterns (00000000 through 11111111 binary, or 00 through FF hexadecimal). Avionics documentation treats the byte as the usual smallest addressable unit of storage: a status discrete packed as one byte, a BITE dump printed as hexadecimal pairs, an 8-bit microcomputer location. A nibble (four bits, one hexadecimal digit) is useful when reading dumps but is not named in current Appendix I.

A word is the native group of bits the processor moves in one data-bus cycle. Word length is a design property, not a universal constant: 8-bit, 16-bit and 32-bit machines all appear in aircraft computers. A 16-bit word holds two bytes; a 32-bit word holds four. Do not confuse CPU word length with the ARINC 429 32-bit transmission word — that is an inter-LRU serial format (Chapter 3), not the width of the microprocessor's parallel data bus.

Hardware, software, CPU and IC

Hardware is the physical equipment: printed-circuit boards, integrated circuits, connectors, backplanes, power-supply modules, crystals, and the line-replaceable unit (LRU) chassis. If you can hold it, it is hardware.

Software is the set of programs and associated data that tell the hardware what to do. On an aircraft computer that includes the operational flight program (OFP), boot firmware, the executive or operating system, and loadable databases. Software has no mass, but it has a part number and a configuration status; unapproved changes are an airworthiness issue treated under topic 5.13. Hardware executes software; software cannot run without hardware. Firmware is software stored in a non-volatile device that the maintainer treats almost like hardware, because it is not supposed to change from flight to flight unless a controlled data load is performed.

The central processing unit (CPU) is the functional heart of the computer. It fetches instructions, decodes opcodes, executes operations, and issues bus-control commands. In Module 5 teaching the CPU is implemented as a microprocessor (MPU) — a CPU on a single chip that still needs external memory and I/O to become a complete computer — or as the CPU core inside a microcontroller. This guide develops the control unit, clock, registers and ALU under topic 5.7; current 5.6(a) provides only the broad computer terminology and technology heading.

An integrated circuit (IC) is a semiconductor die carrying many transistors and passive elements in one package. Memory chips, the microprocessor, bus transceivers and peripheral controllers are all ICs. Scale (SSI, MSI, LSI, VLSI) is topic 5.8. For 5.6(a), recognise that the computer is built from ICs, not from racks of discrete transistor gates.

RAM, ROM and PROM as 5.6(a) terms

The former detailed Appendix I description named three memory terms in 5.6(a). Treat them as vocabulary here; section 7.2 develops operation, access time and limitations.

Random access means the CPU can address location 0000 hexadecimal or location FFFF hexadecimal in one cycle of comparable duration — unlike magnetic tape, which must skip sequentially. Volatile means the stored bits vanish when supply voltage is removed. Those two ideas are independent: RAM is random and (normally) volatile; ROM is random and non-volatile.

Computer technology in aircraft systems

Almost every modern aircraft system that is not purely mechanical contains an embedded computer. Examples a Module 5 candidate should be able to place include the flight management computer (FMC / FMGC) for navigation and performance; air-data / ADIRU processing; electronic engine control / FADEC; flight-control computers on fly-by-wire types; EFIS symbol generators or display units; cabin-systems and information-systems computers; and integrated modular avionics (IMA) cabinets that host several applications on shared computing modules (section 8.3).

These are embedded, real-time machines. They run a defined program, sample sensors and buses on a schedule, and must finish each frame before the next. They are not general-purpose office PCs. Physically they appear as LRUs in racks, as modules on an IMA backplane, or as a microcontroller on a sensor or actuator board. Communication between boxes uses avionics data buses (ARINC 429, 629, 664, MIL-STD-1553B — Chapters 3 and 4). Communication inside a box uses the microprocessor's address, data and control buses. Mixing those two layers is a standard examination trap: a 32-bit ARINC word on a twisted pair is not the CPU data bus.

Microcomputer and microcontroller layout (5.6(b))

A microprocessor is the CPU chip. A microcomputer is a complete computer organised around that chip: the MPU plus external RAM, ROM/PROM, address decoding, bus buffers, clock and I/O adapters on a printed-circuit board or backplane. Classic 8-bit and 16-bit avionics cards look like this. The three buses are visible as PCB tracks.

A microcontroller (MCU) integrates the CPU core, clock generator, RAM, non-volatile program memory, timers, analogue-to-digital converters, serial ports and discrete I/O on a single IC. The external bus may be absent or used only for expansion. Door controllers, proximity-sensor cards, simple actuator loops and many modern sensor heads are microcontrollers. They reduce board area, connector count and power, at the cost of a fixed on-chip memory map.

Two internal organisations appear:

• Von Neumann (Princeton): program and data share one memory and one pair of address/data paths. Simple, but instruction fetches and data reads contend for the same bus (the von Neumann bottleneck).
• Harvard: separate program and data memories, often with separate buses. Many microcontrollers and digital signal processors use Harvard organisation so that an instruction fetch and an operand read can overlap.

Address, data and control buses

A bus is a shared set of conductors. In the classic microcomputer three buses interconnect the CPU, memory and I/O.

Address bus. Unidirectional in a normal CPU-driven cycle: the processor drives a binary address, and memory or I/O decodes it. Direct memory access (DMA), if fitted, is the usual exception — a DMA controller may take the bus and drive addresses while the CPU is held off. Width n bits gives 2^n unique locations. A 16-bit address bus selects 2^16 = 65536 locations. If each location is one byte, that is 64 KiB (64 × 1024). A 20-bit address bus selects 1048576 locations (1 MiB). A 32-bit address bus selects 4294967296 locations (4 GiB). The address bus does not carry the data stored at the location; it only names it. Address lines are usually labelled A0 (least significant) upwards.

Data bus. Bidirectional. During a read, the selected memory or I/O device drives instruction or data bits toward the CPU. During a write, the CPU drives data toward the selected device. Width is the word length moved per cycle: 8, 16 or 32 bits are the usual teaching widths. An 8-bit data bus fetching a 24-bit instruction needs three successive read cycles.

Control bus. A collection of command and timing lines, not a third copy of the data. Typical lines include memory read / memory write (MEMR, MEMW) or a single R/W with a chip-enable; I/O read / I/O write (IOR, IOW) on processors that use isolated I/O (section 7.3); clock distribution; reset; ready/wait (to insert wait states for slow PROM); interrupt request and interrupt acknowledge; and bus request / bus grant for DMA.

Only one device may drive the data bus at a time. Tri-state (three-state) buffers implement that rule: output high, output low, or high-impedance (disconnected). Chip-select and read/write strobes enable exactly one driver. If two drivers oppose each other (bus contention), the result is illegal logic levels, overcurrent and possible IC damage. A floating data bus (nobody driving) is equally undefined; some designs add pull-ups or a default idle device.

Worked address-space example

A B2 card uses a microprocessor with A0–A15 (16-bit address) and D0–D7 (8-bit data). PROM occupies 0000 hexadecimal to 3FFF hexadecimal (16 KiB). RAM occupies 4000 hexadecimal to 4FFF hexadecimal (4 KiB). The remaining map is spare or I/O.

• Total CPU-visible locations: 65536.
• PROM size: 3FFF − 0000 + 1 = 4000 hexadecimal = 16384 bytes = 16K × 8. The PROM chip-select is decoded when A15 and A14 are 00, and the chip itself uses the lower 14 address bits (2^14 = 16384).
• RAM size: 4FFF − 4000 + 1 = 1000 hexadecimal = 4096 bytes = 4K × 8.
• One data-bus cycle moves 8 bits. A 16-bit immediate operand therefore occupies two consecutive addresses and two read cycles.

Address decoding is combinational logic (or a decoder PROM, or a programmable logic device) that asserts chip select (CS) for exactly one device. Overlapping selects cause contention. Gaps in the map are legal; accesses to unpopulated addresses read garbage or trap, depending on the design.

Keep the picture: CPU in the centre, three buses, memory and I/O as slaves. The address bus chooses; the data bus carries the bits; the control bus says whether this cycle is a read, a write, a wait or an interrupt. That layout is what 5.6(b) means by microcomputer architecture. Section 7.2 puts actual RAM and ROM devices on those buses; section 7.3 runs an instruction around them.