1.2 Binary Arithmetic and Signed Number Representation

1.2 Binary Arithmetic and Signed Number Representation

Digital air-data computers, inertial reference systems and flight-control modules do not store a minus sign as a printed glyph. They store signed binary words. The current Appendix I 5.2 heading is simply numbering systems; signed arithmetic is an exam-useful expansion a B2 candidate meets when a two’s-complement data field is decoded, and it is the representation used inside almost every avionics processor ALU. This section covers unsigned addition and subtraction, overflow, sign-magnitude, one’s complement and two’s complement, the n-bit two’s-complement range, and why aircraft data words use two’s complement rather than sign-magnitude.

Unsigned binary addition

Addition is bit-wise from the LSB. A column that sums to 2 or 3 writes 0 or 1 and produces a carry of 1 into the next column.

Worked example — add 0101₂ (5) and 0011₂ (3):

  0101
+ 0011
------
  1000     = 8₁₀

Column by column from the right: 1+1 = 10₂ (write 0, carry 1); 0+1+carry 1 = 10₂ (write 0, carry 1); 1+0+carry 1 = 10₂ (write 0, carry 1); 0+0+carry 1 = 1. Result 1000₂ = 8₁₀. Decimal check: 5+3=8.

A second 8-bit example used on discrete buses: 0010 1101₂ (45) + 0001 0010₂ (18) = 0011 1111₂ (63). If the ICD later treats that byte as two’s complement rather than unsigned, the same bits still mean +63 because the sign bit is 0. The arithmetic did not change; only the interpretation of the MSB changes when the field is declared signed.

Unsigned binary subtraction and borrow

Subtraction uses a borrow of 1 from the next higher column when the subtrahend bit is 1 and the minuend bit is 0.

Worked example — 1101₂ (13) minus 0110₂ (6):

  1101
- 0110
------
  0111     = 7₁₀

Decimal check: 13−6=7, so 0111₂ is correct. In hardware, subtraction is rarely a separate borrow circuit. The ALU adds the two’s complement of the subtrahend to the minuend. That single fact is why two’s complement dominates processor data paths and, by extension, many avionics integer fields.

Overflow in a fixed-width word

Avionics registers have a fixed width: 8, 16 or 32 bits in processors; 19 data bits in an ARINC 429 word. Overflow occurs when the true mathematical result cannot be represented in that width.

Unsigned 4-bit example: 1101₂ (13) + 0100₂ (4) = 10001₂. Only four bits fit, so the stored result is 0001₂ (1) and a carry-out of 1 is lost unless a status flag captures it. Decimal 13+4=17 exceeds the 4-bit unsigned maximum of 15 (2⁴ − 1).

For signed two’s-complement addition, overflow is not the same as carry-out. Overflow occurs when two numbers of the same sign produce a result of the opposite sign:

• Two positives yielding a negative bit pattern
• Two negatives yielding a positive bit pattern

Adding +7 and +1 in 4-bit two’s complement: 0111 + 0001 = 1000, which is −8, not +8. Carry-out is 0, but overflow is 1. A technician who reads a wrapped two’s-complement air-data increment as an unsigned integer will report an impossible value on the BITE page.

Hardware overflow detection on a two’s-complement adder is the exclusive-OR of the carry into the sign bit and the carry out of the sign bit. If those two carries differ, the sign bit is wrong and overflow has occurred. That is a different flag from the unsigned carry flag, and mixing the two is an examination trap.

Memorise the n-bit two’s-complement range: −2^{n−1} through +2^{n−1} − 1. For 8 bits that is −128 to +127, not −127 to +127. The extra negative code is the pattern 1000 0000₂.

Sign-magnitude representation

The MSB is the sign (0 = positive, 1 = negative); the remaining bits are the ordinary binary magnitude.

4-bit examples:

• +5 = 0101
• −5 = 1101

That encoding is easy to read on a whiteboard and hostile in silicon:

1. Two zeros: +0 = 0000 and −0 = 1000. Comparators and data-valid tests become ambiguous: is a zero velocity word a true stop, or a negative-zero artefact?
2. Adder complexity: an ALU must inspect both signs and choose add or subtract, then possibly correct the sign of the result. Extra gates mean extra delay and extra certification evidence.
3. Asymmetric path for addition versus subtraction, so timing analysis cannot treat every integer operation as the same adder cycle.

Sign-magnitude still appears in some mantissa encodings and in human-readable ICDs that say a discrete sign bit accompanies an unsigned magnitude. It is not the default for integer data words on modern processors.

One’s complement representation

Negative values are the bitwise inversion of the positive pattern. +5 = 0101; −5 = 1010. The n-bit range is −(2^{n−1}−1) to +(2^{n−1}−1), again with two zeros (0000 and 1111). Addition requires an end-around carry: any carry-out of the MSB is added back into the LSB. That extra sequential step is unwelcome in a high-speed, deterministic avionics ALU that must finish in a known number of clock cycles.

One’s complement is worth recognising so you do not stop after the invert step when a question asks for two’s complement. Invert-only is one’s complement; invert-then-add-1 is two’s complement.

Two’s complement — the avionics default

To form −X in n bits:

1. Write the n-bit representation of +X, zero-padding on the left.
2. Invert every bit (this is the one’s complement).
3. Add 1, ignoring carry-out of the MSB.

Worked example — 4-bit −5

• +5 = 0101
• Invert = 1010
• Add 1 = 1011

Check: 1011₂ as unsigned is 11; as 4-bit two’s complement it is 11 − 16 = −5, because the sign bit carries weight −2³ = −8 and the remaining bits are +2 +1 = +3, total −8+3 = −5. Equivalent test: 0101 + 1011 = 10000₂, which truncated to 4 bits is 0000, so the pair are additive inverses.

Worked example — 8-bit −1 and −128

• +1 = 0000 0001; invert 1111 1110; add 1 = 1111 1111 (FF hex). So an 8-bit two’s-complement field of FF means −1, not unsigned 255, if the ICD says the field is signed.
• The most negative 8-bit value is 1000 0000 = −128. Inverting and adding 1 returns 1000 0000: there is no +128 in 8-bit two’s complement, which is the asymmetry you accept in exchange for a unique zero.

Worked addition of unlike signs

8-bit +13 − 6 via two’s complement:

• +13 = 0000 1101
• −6: invert 0000 0110 → 1111 1001, plus 1 → 1111 1010
• Sum: 0000 1101 + 1111 1010 = 1 0000 0111. Drop the carry-out: 0000 0111 = +7

Decimal check: 13−6=7. Overflow is 0 because the operands had different signs; different-sign adds cannot overflow in two’s complement (the result magnitude is smaller than the larger operand).

Why avionics data words use two’s complement

1. Single representation of zero (all bits 0). An IRS velocity of zero, a sidestick residual of zero, or a no-increment delta is an unambiguous all-zero word. Sign-magnitude’s −0 cannot appear.
2. Same adder for every integer operation. The full-adder silicon that adds two positive bytes also adds a negative two’s-complement byte. Subtraction is A + (invert(B) + 1). Gate count, timing closure and DO-178C / ED-12C evidence all shrink when there is one integer datapath.
3. Overflow detection is local (XOR of the two sign-bit carries) and does not require inspecting operand signs in a separate comparator tree.
4. Bus and BITE readability with one rule: if the MSB is 1, the stored value is negative; recover the magnitude by two’s-complementing again (invert, add 1).

A sign-magnitude ARINC payload would need a separate sign discrete or an SSM-like flag for every numeric parameter. Two’s complement folds the sign into the same field the adder already uses. That is why air-data increments, inertial velocities and many control-surface command words are two’s-complement integers (scaled by a documented resolution). The ARINC 429 label remains an unsigned octal field and is not a signed quantity; do not two’s-complement a label.

Exam traps

• Treating 1000₂ in 4-bit two’s complement as −0 (sign-magnitude thinking). It is −8.
• Quoting the 8-bit signed range as −127 to +127 (that is sign-magnitude and one’s complement). Two’s complement is −128 to +127.
• Calling carry-out overflow on a signed add. Check sign agreement, not the carry flag alone.
• Stopping after inversion when asked for two’s complement (that answer is one’s complement: 1010 for −5 in 4 bits, not 1011).
• Reading a BITE hex word FF as unsigned 255 when the ICD says 8-bit two’s complement (−1).
• Two’s-complementing the most negative value and expecting a positive result. In n bits, invert-and-add-1 of 1000…0 returns itself.

Module 5 papers (B2: 72 questions / 90 minutes; about 75 seconds each; 75% pass; three-option live paper; no essay) reward mechanical conversion: write the bits, invert, add 1, expand using sign-bit weight −2^{n−1}. Do not invent a decimal minus-sign bit of weight −1.