6.3 Asynchronous and Synchronous Counters and Logic-Diagram Interpretation

6.3 Asynchronous and Synchronous Counters and Logic-Diagram Interpretation

Appendix I 5.5(a) is level 2 for B1 and B2/B2L. Binary counters are taught here as a practical sequential application of the bistables in section 6.1, not as a separately printed current syllabus bullet. Appendix I 5.5(b), interpretation of logic diagrams, is knowledge level 2 for category B2/B2L only. B1 is not required on 5.5(b). A B2 candidate must therefore be able to read a mixed drawing that contains gates, bubbles, NAND equivalents, and sequential blocks (flip-flops, latches, counters, registers) and state in English when the output asserts. Module 5 remains multiple-choice only (B2 72/90, B1 40/50, 75% pass, no essay).

Ripple (asynchronous) counters

A ripple or asynchronous binary counter is a chain of T flip-flops (or JK cells with J = K = 1) in which only the first stage is clocked by the incoming pulse train. Q of stage 0 clocks stage 1, Q of stage 1 clocks stage 2, and so on. Each stage divides by two, so four stages form a MOD-16 counter that cycles 0000₂ through 1111₂ and rolls over. The count advances on the edge that each stage actually sees, which is delayed from the input clock by the propagation delay of every previous flip-flop. The 1s 'ripple' along the chain — that is the name.

Because the bits do not change at the same instant, the parallel outputs pass through brief illegal codes. Example: 0111₂ (7) to 1000₂ (8). Stage 0 toggles 1→0 first, so the word is momentarily 0110₂ (6); then stage 1 toggles, giving 0100₂ (4); then stage 2 toggles, giving 0000₂ (0); then stage 3 toggles, giving 1000₂ (8). A combinational decoder attached to those pins can therefore produce a glitch on the 'count = 8' line and on several other lines during the ripple. On an aircraft, decoding a ripple counter to fire a one-shot (store a BITE event, step a sequencer) is unsafe unless the decoder is strobed after the ripple has died. Asynchronous clear of all stages to 0000 is still useful as a maintenance reset.

Synchronous counters

A synchronous counter ties every CLK pin to the same incoming clock. Combinational logic looks at the present Q bits and drives T (or J/K) of each stage so that the next edge produces the correct next binary word. For an up-counter:

• Stage 0: T0 = 1 (always toggles).
• Stage 1: T1 = Q0 (toggle when bit 0 is 1).
• Stage 2: T2 = Q0 AND Q1.
• Stage 3: T3 = Q0 AND Q1 AND Q2.

All bits that must change do so on the same edge, so the illegal intermediate codes of the ripple chain do not appear (only a common CLK-to-Q delay remains). The extra AND gates are the price. Aircraft event counters, frame counters on a discrete serialiser, and clock-divider trees that must be decoded cleanly are drawn synchronous. A drawing that shows CLK of FF1 coming from Q0, not from the common clock, is ripple — expect glitches if you decode it.

5.5(b) — how to read a logic diagram (B2)

A logic diagram is not a wiring schematic of pins and loom numbers. It is a functional drawing of gates and sequential cells. The B2 method is mechanical. Do not guess from the title block.

Step 1 — Name the output of interest. Lamp driver, horn, start-valve solenoid, computer enable, 'warning valid'. Write its active level. A bar over the name, a trailing asterisk, or a bubble on the driven pin means the output is asserted low.

Step 2 — Walk the enable path backwards. An AND asserts only when every input is in its asserting state. An OR asserts when any input is in its asserting state. A NAND is an AND with a bubble on the output (or an OR of inverted inputs, by De Morgan). NOR is the opposite. At each pin, ask: is there a bubble?

Step 3 — Honour bubbles as inversion. A bubble on an AND input means that pin is active-low: the AND treats a 0 on the arriving net as a logical 1 at the gate. A bubble on an AND output means the function is NAND. Two bubbles in series on the same net cancel. Aircraft discretes are often active-low (ground to assert) so bubbles are common; ignoring one inverts the whole interlock.

Step 4 — Rewrite NAND-NAND as AND-OR. Discrete IC families are often NAND-only. Two NAND gates feeding a third NAND implement (A AND B) OR (C AND D):

(A NAND B) NAND (C NAND D) = NOT[ NOT(A AND B) AND NOT(C AND D) ] = (A AND B) OR (C AND D).

That De Morgan identity is the NAND equivalent of a two-term sum of products. On a crowded drawing, pencil the AND-OR form in the margin so the enable path is in aircraft English ('down-and-locked AND doors closed') rather than a nest of NANDs.

Step 5 — Separate sequential from combinational blocks. Combinational clouds have no clock triangle and no cross-coupled memory: their output is a function of present inputs after a few gate delays. Sequential blocks show a CLK triangle (flip-flop, register, synchronous counter), an enable without a triangle (latch), or cross-coupled NAND/NOR (SR). A sequential Q that feeds back into the combinational cloud is memory in the enable path — typically a cutout, a latched fault, or a one-shot. Mark it; it will still be true after the original discrete has gone.

Step 6 — Write the Boolean, then the English. Substitute the net names from the drawing. Check the SR forbidden case if an SR is present: can S and R be true together? Check hold versus shift if a register is present. Check ripple versus common clock if a counter is present.

Worked walkthrough: landing-gear warning horn with cutout latch

The diagram (block below) is a teaching interlock, not a copy of one type's AMM page. The output of interest is HORN, active-high into a driver. Trace backwards.

HORN is the output of AND1. AND1 has three inputs:

1. Gear not down-and-locked (active-high discrete GEAR_NOT_DN). If this pin is 0, the horn cannot sound — combinational inhibit.
2. OR1, which is throttle idle OR flaps in the landing range. Either condition says 'the aeroplane should have gear down if we are in this configuration'.
3. NOT Q of the cutout latch — a bubble (inverter) on the third AND input. When the latch is reset (Q = 0), NOT Q = 1 and this input enables the AND. When the latch is set (Q = 1), NOT Q = 0 and the AND is inhibited even if gear is still up and the throttles are idle.

So the combinational enable is:

HORN = (gear not down-and-locked) AND (throttle idle OR landing flaps) AND (cutout latch not set).

The sequential block is an SR latch. Set comes from the horn-cutout pushbutton (momentary). Reset comes from gear down-and-locked. The crew can silence the horn with the cutout PB while still in the air with gear up; the latch holds that silence after the PB is released (memory). When the gear finally locks down, Reset clears the latch so the next approach has a live horn. Because Set is a momentary PB and Reset is a gear discrete, the drawing must not allow both to sit at 1 as a steady state — the PB is sprung and the two events are operationally exclusive; if a fault grounded both nets, the SR would enter the forbidden row of section 6.1.

NAND equivalent of OR1 and AND1. If the card is built from NAND gates only, De Morgan gives the same functions with extra bubbles. Idle OR flaps is identical to a NAND whose two inputs carry bubbles: A OR B equals NOT(NOT A AND NOT B). The three-input AND1 is a NAND followed by an inverter (a bubble on the NAND output, then one more inversion), or a NAND driving HORN if HORN is allowed to be active-low. The function does not change; only the drawing changes. A B2 reader who stops at 'I see three NAND symbols' has not interpreted the diagram. Translate to AND-OR, then to English.

Enable-path faults the method finds:

• Horn dead with gear up and idle: check GEAR_NOT_DN discrete, OR1 inputs, the bubble on the cutout path (a missing inverter would require Q = 1 to sound the horn — opposite of the design), and AND1 itself.
• Horn will not silence: cutout PB not reaching S, or the latch failed in Reset (Q stuck 0).
• Horn stays silent after gear-down then a later go-around with gear up: Reset net stuck asserted, or Q stuck 1 (latch never cleared).
• Brief horn beep while the gear is travelling: if a ripple counter elsewhere encodes 'gear in transit' and is decoded combinationally, expect a glitch; a synchronous encode, or a latch that Sets only when the condition is stable, removes it.

That is 5.5(b): trace enables, honour bubbles, rewrite NAND equivalents, and say which blocks are sequential. B1 candidates are not examined on this interpretation skill; B2/B2L are, at level 2.