2.3 Analogue-to-Digital Converters

2.3 Analogue-to-Digital Converters

Section 2.1 established why aircraft parameters must be sampled and quantised. This section examines how an analogue-to-digital converter (the electronic ADC) performs that quantisation, what each common architecture can and cannot do, and where those limitations appear in air-data computers and engine-sensor channels. The current Appendix I topic 5.3 is Data conversion. The analogue/digital data, converter operation and application, inputs, outputs, and limitations listed here come from the former detailed Appendix I description and remain useful study scope. Category B2 knowledge is level 2; Category B1 is level 1.

The name ADC is overloaded in aviation. In electronics it means analogue-to-digital converter. In air-data it means air-data computer. This section uses “analogue-to-digital converter” for the electronic function and “air-data computer” for the line-replaceable unit that contains several such converters plus computation. Confusing the two on a defect report sends the wrong shop.

Every analogue-to-digital converter has the same logical inputs and outputs. Inputs are a conditioned analogue voltage (or current), a stable reference, analogue and digital supplies, a convert-start or clock, and often a sample-and-hold control. The output is an $n$-bit parallel or serial digital word, sometimes with an end-of-conversion flag. All of the architectures below implement the same mapping from a held voltage onto one of $2^n$ codes; they differ in how they search for that code and therefore in speed, power, resolution, and noise rejection.

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Flash (Parallel) Converters

A flash converter uses $2^n - 1$ analogue comparators. A resistor ladder derives $2^n - 1$ equally spaced reference taps from $V_{\text{ref}}$. Each comparator decides, in one glance, whether the held input is above or below its tap. A priority encoder then turns the thermometer-coded comparator bank into a binary word. Conversion occupies essentially one comparator decision time plus the encoder delay — tens of nanoseconds on fast parts.

The limitation is brute force. An 8-bit flash converter needs 255 comparators; a 12-bit flash converter would need 4 095. Power, die area, input capacitance, and comparator offset matching become prohibitive. Flash devices in avionics therefore appear where speed is mandatory and bit depth can stay modest: some video, radar-pulse, or wide-band vibration paths, not the 12- to 16-bit air-data and engine analogue suite. Comparator offsets also create sparkle codes (wild isolated errors) if the thermometer pattern is not cleaned by encoding logic.

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Successive-Approximation Converters

The successive-approximation register (SAR) converter is the avionics workhorse. It contains a DAC, a single comparator, and a logic register. Conversion is a binary search:

1. The sample-and-hold freezes $V_{\text{in}}$.
2. The register sets the most-significant bit and the internal DAC produces mid-scale.
3. The comparator tests whether $V_{\text{in}}$ is above or below that trial voltage.
4. The bit is kept or cleared, the next bit is set, and the test repeats.
5. After $n$ comparisons the register holds the digital word.

Conversion time is therefore about $n$ clock periods plus acquisition time of the sample-and-hold. A 12-bit SAR at a $1\text{ MHz}$ bit clock needs roughly $12\text{ }\mu\text{s}$ plus acquisition — fast enough for air-data and most engine parameters sampled at a few hundred hertz, and far cheaper in power than a 12-bit flash converter. The internal DAC must itself be monotonic; if it is not, the search can skip codes and the external analogue-to-digital converter will show missing codes.

SAR converters do not inherently reject $400\text{ Hz}$ ripple. Whatever voltage is held at the sampling instant, including interference, becomes the digital word. Anti-alias filtering and a quiet analogue reference remain mandatory. Aperture jitter on the sample command turns a steep analogue slope into an amplitude error, which matters more on vibration channels than on a slow oil-temperature probe.

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Dual-Slope and Integrating Converters

A dual-slope (integrating) converter charges an integrator from the unknown input for a fixed time $T_{\text{int}}$, then discharges the integrator from a precision reference of opposite polarity and measures the de-integrate time $T_{\text{de}}$. The ratio of the two times is the ratio of $V_{\text{in}}$ to $V_{\text{ref}}$, independent of the exact integrator capacitor and of the clock frequency provided the same clock times both intervals.

The great operational advantage is interference rejection. Periodic noise that completes an integer number of cycles during $T_{\text{int}}$ integrates toward zero. Designers therefore choose $T_{\text{int}}$ as a multiple of the period of the expected interferer — $50\text{ Hz}$ or $60\text{ Hz}$ on ground equipment, and often a multiple related to $400\text{ Hz}$ on aircraft when that ripple is the threat. The price is speed. A 50 Hz rejection window is already $20\text{ ms}$ of integrate time before de-integrate even begins, so dual-slope converters are reserved for slow, high-accuracy measurements: some fuel-quantity, precision temperature, or built-in calibration channels, not wide-band vibration or video.

Single-slope and multi-slope variants exist; Module 05 expects the dual-slope story: integrate the unknown, de-integrate the reference, trade time for noise rejection and accuracy, accept a long conversion.

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Sample-and-Hold

A sample-and-hold (or track-and-hold) is not optional decoration. During the sample (track) interval an analogue switch charges a hold capacitor from the anti-aliased input. During hold the switch opens and a high-impedance buffer presents a frozen voltage to the converter. If the analogue input were allowed to move while a SAR walked through its bits, later bits would be decided on a different voltage than earlier bits and the word would be meaningless. Flash converters are fast enough that a dedicated hold is sometimes absorbed into the comparators, but air-data and engine SAR channels always document an acquisition time, a hold step, and droop.

Hold step (pedestal) is a small voltage jump when the switch opens, caused by charge injection. Droop is the slow discharge of the hold capacitor through leakage during a long conversion. Both must stay well below one LSB. A leaky hold capacitor on a slow dual-slope conversion is a classic accuracy fault that looks like a drifting sensor.

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Conversion Time versus Resolution, and Missing Codes

For flash converters, raising resolution from $n$ to $n+1$ bits roughly doubles the comparator count ($2^{n+1}-1$ versus $2^n-1$). Power and area explode; conversion time stays short. For SAR converters, each extra bit adds one comparison period, so conversion time grows linearly with $n$, but the internal DAC must be built to the new resolution. For dual-slope converters, extra bits mean a finer time measurement of $T_{\text{de}}$ and usually a longer de-integrate, so conversion time grows again.

That is the syllabus trade-off: faster architectures at a given bit depth cost hardware; finer resolution at a given architecture costs time (and, for flash, an impractical comparator farm). Designers pick flash for speed, SAR for general avionics parameters, and integrating types for slow precision with interference rejection.

A missing code occurs when some binary number never appears at the output no matter how the analogue input is swept. The usual cause is differential non-linearity more negative than $-1\text{ LSB}$: a step in the transfer function is so wide that an adjacent code is skipped. Missing codes destroy the assumption that every digital increment corresponds to one analogue increment. Closed-loop control and fine air-data resolution both suffer. Monotonicity of the internal DAC (in a SAR) and comparator spacing (in a flash converter) are the manufacturing controls; in service, a converter with missing codes is a failed or out-of-tolerance part, not something software can “fill in” with integrity.

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Aircraft Applications: Air-Data Computers and Engine Sensors

Air-data computers concentrate many analogue-to-digital converter channels. Conditioned pitot and static pressures, angle of attack, and total air temperature are sampled through anti-alias filters and sample-and-holds, typically by SAR converters at resolutions of 12 bits or more. The digital words feed the air-data algorithms that produce computed airspeed, Mach, pressure altitude, and true airspeed for displays, flight-control computers, and transponders. A missing-code or reference fault on the pitot channel is an airspeed integrity problem, not a “display fault”, even though the crew sees it on the airspeed tape. Conversion time must finish well inside the air-data iteration period; a dual-slope converter on the primary pitot path would be too slow for modern control and display refresh, which is why integrating types, if used at all, sit on slow monitors or calibration references.

Engine sensors feeding a FADEC or engine-indication computer include speeds (after analogue tachometer conditioning), exhaust-gas or turbine temperatures, oil pressure and temperature, fuel flow, and vibration. Fast channels (vibration, some speed pulses after analogue shaping) may use faster SAR or limited flash conversion. Slow thermal channels can tolerate longer conversion and may benefit from integrating rejection of engine-bay electromagnetic interference. In all cases the analogue-to-digital converter sees a conditioned voltage: cold-junction compensation, bridge excitation, and anti-alias filtering are part of the input. Replacing a thermocouple without confirming the converter reference and the sample-and-hold supplies will not restore a correct digital exhaust-gas-temperature word.

[!WARNING] Treat the convert-start timing as part of the measurement. If two engine channels are not sampled at the documented instant, computed differences (for example, split indications) can appear even though each sensor is within its own analogue tolerance. Intermittent convert-start or a sample-and-hold stuck in track produces exactly that class of defect.

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Worked Numerical Example: SAR Timing and a Missing-Code Check

An air-data pitot channel uses a 12-bit SAR converter clocked at $800\text{ kHz}$ bit rate. Acquisition time of the sample-and-hold is $2.0\text{ }\mu\text{s}$.

Step 1 — Conversion time

$T_{\text{conv}} \approx 12 \times \frac{1}{800\times 10^3}\text{ s} + 2.0\text{ }\mu\text{s} = 15.0\text{ }\mu\text{s} + 2.0\text{ }\mu\text{s} = 17.0\text{ }\mu\text{s}$

Step 2 — Maximum sampling rate if conversion must finish inside one period

$f_{s,\max} \approx \frac{1}{17.0\text{ }\mu\text{s}} \approx 58.8\text{ kHz}$

The air-data iteration may only need a few hundred hertz, so the converter is not the bottleneck; the anti-alias filter and the processor load are. The same 12-bit conversion implemented as dual-slope with a $2.5\text{ ms}$ integrate window would need several milliseconds and could not support a fast control loop.

Step 3 — Missing-code implication

If a swept analogue input never produces digital code $2048$ (mid-scale) while $2047$ and $2049$ appear, the converter has a missing code at the major carry. Differential non-linearity at that transition is worse than $-1\text{ LSB}$. The airspeed word will jump across the missing code as pitot voltage rises through mid-scale, which is an integrity defect, not a probe calibration offset.

Step 4 — Flash hardware cost for the same 12 bits

A flash implementation would need $2^{12}-1 = 4095$ comparators. That is why the air-data computer uses a SAR converter: 12 bits are required, but a few tens of microseconds are acceptable.

[!NOTE] Inputs, outputs, and limitations again travel together. The input is a held, anti-aliased analogue voltage plus a reference. The output is an $n$-bit word and an end-of-conversion flag. The limitations — conversion time, missing codes, droop, aperture jitter, and the architecture’s interference behaviour — decide whether that word is fit for an air-data computer or an engine-sensor channel.