7.3 Microprocessor Operation, Instruction Cycles and I/O

7.3 Microprocessor Operation, Instruction Cycles and I/O

Topic 5.7 is examined at knowledge level 2 for category B2/B2L only. The current text gives only the Microprocessors heading and level; the control and processing unit, clock, register and ALU come from the former detailed description. That former 5.6(b) detail also named single- and multi-address instruction words and typical memory operation, which become concrete once you watch one instruction travel around the architecture of section 7.1. Isolated versus memory-mapped I/O is standard teaching that sits on the same buses. Categories A, B3 and B1 are not examined on 5.7 or 5.6(b). The live paper remains three-option multiple-choice (B2 72 questions in 90 minutes, 75% pass, no negative marking, no essay); practice items here use four options. OpenExamPrep publishes this as independent preparation, not as an EASA document.

Function of the microprocessor

A microprocessor is a programmable IC that:

1. Fetches instruction bytes from memory (usually ROM or flash) at the address held in the program counter.
2. Decodes the opcode to decide which operation and which addressing mode.
3. Executes that operation using the ALU and registers, generating control-bus signals for further memory or I/O cycles if operands live off-chip.
4. Repeats, unless halted or reset.

It does not know fuel flow or localiser deviation. Those meanings exist in software. The silicon only moves bits, adds, compares and jumps.

Two internal blocks implement that loop.

Control unit (CU) — the sequencer. It contains instruction-decode logic (hardwired or microcoded), the state machine that runs fetch–decode–execute, and the drivers for MEMR, MEMW, IOR, IOW and register-enable pulses. When the opcode says JMP, the CU loads the program counter from the address field instead of merely incrementing it. When the opcode says ADD, the CU steers operands to the ALU and writes the result back. The control unit does not add two numbers; it decides when the ALU and the buses may act.

Processing unit / ALU (arithmetic logic unit) — the combinational datapath. Arithmetic: add, subtract, increment, decrement; some devices multiply or divide. Logic: AND, OR, XOR, NOT, shifts and rotates, and compare (a subtract that only affects flags). After each relevant operation the ALU updates a status (flags) register: Z (zero), C (carry/borrow), N or S (negative/sign), V or O (overflow), sometimes half-carry or parity. Conditional jumps test those flags (JZ, JC). The ALU does not store the program; it processes words that registers or memory present for one clocked operation.

Clock

A clock is a periodic square wave, usually from a quartz crystal and oscillator circuit, that synchronises every sequential element: program counter, instruction register, bus-cycle state machine, and peripherals that derive baud rates from the same source. The clock does not itself perform arithmetic.

Clock frequency f and period T = 1/f. An 8 MHz clock has T = 125 ns. If a particular instruction needs four clock cycles (datasheets may count machine cycles, T-states or S-states — read the wording), that instruction occupies 4 × 125 ns = 500 ns. Wait states stretch the cycle when memory is slow (section 7.2). Aircraft computers also use derived clocks to timestamp frames, but the 5.7 meaning is the CPU timing reference. Over-clocking is not an approved maintenance action; crystal frequency is a design property.

Reset holds the CPU in a defined state and, when released, typically loads the program counter from a reset vector in non-volatile memory so that execution starts at a known boot address, not at a random RAM address.

Registers

A register is a small, extremely fast store inside the CPU. Access time is a fraction of an off-chip memory cycle, which is why operands are brought into registers before a burst of ALU work. Registers are volatile: a power interrupt loses them, which is one reason a reset vector in ROM-family memory is mandatory.

Fetch, decode, execute

One instruction cycle has three phases.

Fetch. The CU copies PC into MAR and onto the address bus. Control asserts memory-read. ROM or flash drives the opcode onto the data bus into MDR and then IR. The PC increments by one byte (or by the instruction size if the machine fetches whole words). If the instruction is multi-byte, further fetch cycles collect address or immediate fields.

Decode. The CU inspects IR. Combinational logic or a microcode lookup determines the ALU operation, which registers are used, whether another memory cycle is needed, and whether the PC will be replaced.

Execute. Examples:

• Register–register ADD: the ALU adds two registers, writes the result, updates flags. No extra bus cycle.
• ADD from memory (single-address): MAR loads the operand address from the instruction; a read cycle brings the operand to the ALU with the accumulator; ACC becomes ACC + M[addr]; flags update.
• Store: a register or ALU value goes to MDR; a write cycle occurs at the operand address.
• JMP: PC is loaded from the address field. The next fetch is from the target, not from the next sequential location.
• Conditional jump: as JMP if the tested flag is set; otherwise the PC remains sequential.

Then the loop repeats. Interrupts finish the current instruction. If interrupts are enabled, the CU stacks the PC (and often the flags) and loads a vector address — a hardware-forced jump to a service routine. Returning from the routine pops the stacked PC so the interrupted program resumes.

Worked timing example

Clock 8 MHz (T = 125 ns). An ADD that uses one opcode fetch (1 cycle), a two-byte address fetch (2 cycles), an operand read (1 cycle) and an ALU step (1 cycle) occupies 5 cycles = 625 ns. A 150 ns PROM on a 125 ns T-state needs at least one wait state on every memory read, stretching the same instruction further. Access time from section 7.2 and the clock from 5.7 are the same story: slow silicon plus a fast crystal without wait states yields wrong opcodes, not a tidy halt.

Single-address and multi-address instruction words (5.6(b))

An instruction word contains an opcode field and, for most instructions, one or more address (or register-select) fields.

Single-address instruction. Opcode plus one memory address. The other operand is implied, almost always the accumulator. Example: ADD 2000 meaning ACC becomes ACC + Memory[2000]. The instruction word must be wide enough for opcode plus address. On an 8-bit data bus a compact opcode and a 16-bit address cannot fit in one byte, so the instruction is stored as three bytes (opcode, address low, address high) and needs three fetch cycles. Single-address machines keep hardware simple: one MAR path, one accumulator.

Two-address instruction. Opcode plus two locations or registers, typically destination and source: MOV R1, R2 or ADD dest, src meaning dest becomes dest + src. More encoding bits, fewer implied operands, often fewer instructions for a given job.

Three-address instruction. Opcode plus dest, src1 and src2: ADD R1, R2, R3 meaning R1 becomes R2 + R3. Common in RISC-style register files; rare as a single memory-to-memory word on small avionics MPUs because the word would be very wide or would occupy many bytes.

Zero-address (stack) instruction. Opcode only; operands come from the top of the stack (ADD pops two, pushes one). The address field disappears.

Multi-address in the former detailed scope means instructions that encode more than one explicit address, as opposed to the single-address accumulator machine. Multi-address words are longer (more bits or more bytes) and may need more fetch cycles on a narrow data bus. That is a limitation: throughput falls if every ADD drags two 16-bit addresses over an 8-bit bus. The advantage is programming convenience and fewer implied side-effects.

Immediate, direct, indirect and indexed addressing modes sit on top of those formats. The address field may be the operand itself (immediate), the location of the operand (direct), the location of a pointer (indirect), or a base plus offset (indexed). Typical memory operation is still the read/write cycle of section 7.2; addressing mode only changes how MAR is calculated.

Isolated I/O versus memory-mapped I/O

Peripherals (UART, discrete latch, ARINC encoder, ADC data register) must be addressable.

Isolated (I/O-mapped) I/O. A separate port address space. Dedicated instructions (IN, OUT) and dedicated control lines (IOR, IOW). Memory strobes stay inactive during those cycles. Advantage: the whole memory map remains available for RAM and ROM; I/O ports cannot be confused with program space. Limitation: extra instructions and extra pins; not every microprocessor provides them.

Memory-mapped I/O. Peripheral registers occupy ordinary memory addresses. A store to FF00 hexadecimal may write the UART data register; a load reads it. Ordinary LDA, STA or MOV suffice. Advantage: any memory-reference instruction, including those that operate through the ALU, can touch I/O; simpler decoding on many microcontrollers. Limitation: those addresses are lost to RAM/ROM; an accidental jump into the I/O region executes garbage; write protection of program memory does not automatically protect I/O registers.

Microcontrollers usually memory-map on-chip peripherals. Board-level microcomputers with 8080/8086-family CPUs often use isolated I/O for discrete cards and memory-mapping for dual-port display buffers. Either way the device still sits behind an address decoder and tri-state buffers. Bus contention, wait states and chip-select overlap remain the maintenance faults.

A B2 technician reading a schematic should ask three questions of every rectangle on the CPU bus: is it memory or I/O; which addresses select it; is the instruction that talks to it a memory reference or an IN/OUT? That reading, plus fetch–decode–execute, is the operational content of 5.6(b) and 5.7 together.