5.2 Boolean Algebra, De Morgan Theorems and Logic Simplification

5.2 Boolean Algebra, De Morgan Theorems and Logic Simplification

The pre-12 June 2024 detailed description for 5.5(a) named equivalent circuits as well as symbols and tables; current Appendix I retains the broader “Identification and applications” wording. Boolean algebra is the language used to prove that two drawings implement the same combinational function. The output still depends only on present inputs; simplification never turns a gate network into a flip-flop or a counter. Those sequential devices belong in a later chapter.

The aim on the aircraft and in the examination is practical: fewer packages, the same truth table, and a schematic that can be read in either distinctive-shape or IEC form. OpenExamPrep presents these identities as independent study material for Module 5; they are standard Boolean results, not an official EASA partnership claim.

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Core identities

Write 1 for HIGH and 0 for LOW in positive logic. Product is AND; sum is inclusive OR; a prime marks inversion. The identities below are used constantly when a wiring diagram is redrawn as a single gate.

Worked absorption. Y = A + A·B. Factor A: Y = A · (1 + B). Null law: 1 + B = 1, so Y = A · 1 = A. Electrically, if A is already 1, the extra AND term cannot change the OR. If A is 0, both terms are 0. Either way the output follows A, so the AND gate is redundant.

Worked distribution the other way. Y = (A+B)·(A+C). Expand: Y = A·A + A·C + B·A + B·C = A + A·C + A·B + B·C. Absorb A·C and A·B into A: Y = A + B·C. That identity is the dual of the ordinary distributive law and is a frequent examination rewrite: an AND of two OR terms with a shared literal collapses to that literal ORed with the product of the others.

Worked cancellation. Y = A·B + A·B′. Factor A: Y = A · (B + B′) = A · 1 = A. The two AND terms are complementary in B, so they reconstruct A. A candidate who treats Boolean + as arithmetic plus and writes 2A has left the algebra.

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De Morgan’s theorems

Two statements, used in both directions:

1. The complement of a product is the sum of the complements: (A·B)′ = A′ + B′
2. The complement of a sum is the product of the complements: (A+B)′ = A′ · B′

In words that match the hangar drawings:

• A NAND equals an OR with both inputs inverted.
• A NOR equals an AND with both inputs inverted.
• Inverting both inputs of AND yields NOR, because A′ · B′ = (A+B)′.
• Inverting both inputs of OR yields NAND, because A′ + B′ = (A·B)′.

Two-input proof by exhaustive table

Columns (A·B)′ and A′+B′ are identical, so NAND = OR with inverted inputs. Columns (A+B)′ and A′·B′ are identical, so NOR = AND with inverted inputs. The same pattern extends to three or more inputs: invert the operator (AND ↔ OR) and invert every literal.

Why the AND-with-inverted-inputs drawing is NOR

An AND gate with bubbles already on both inputs computes A′ · B′. De Morgan says that product of complements is (A+B)′ — the NOR function. On an IEC rectangle that network is either & with a circle on each input, or ≥1 with a circle on the output. Both drawings have the same four-row table. Treating input bubbles as decoration, or assuming any bubble turns AND into NAND, is the classic trap: NAND is AND with the bubble on the output, not on the inputs.

Why the OR-with-inverted-inputs drawing is NAND

An OR gate with bubbles on both inputs computes A′ + B′ = (A·B)′. That is NAND. IEC may show ≥1 with input circles, or & with an output circle. Same table.

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Bubble pushing

Bubble pushing is De Morgan applied to a drawing without rewriting the algebra by hand:

• Pushing a bubble through a gate changes AND into OR or OR into AND, and adds or removes a bubble on every pin of that gate (all inputs and the output).
• Two bubbles on the same net cancel (double inversion).
• A bubble may be drawn on either end of a wire; it still inverts that signal once.

Example. Start with NAND: AND shape, bubble on the output. Push the output bubble through the gate: the AND becomes OR, the output bubble disappears, and a bubble appears on each input. The result is OR with both inputs inverted — the De Morgan equivalent already proved. Pushing again restores the original NAND.

Example with mixed polarity. A three-input AND feeding a lamp, with one active-low discrete, is drawn as AND with a single input bubble. That is not NOR. Only all inputs inverted would convert AND into NOR. One inverted input is a different function: Y = A′ · B · C, which is 1 only when A is LOW and B and C are HIGH.

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Examination trap equivalents

XOR is the usual confusion with OR because both are 1 for 01 and 10. They disagree on 11: OR is 1, XOR is 0. Substituting an OR symbol into a parity or comparator drawing changes the table.

Simplification must preserve the table. Replacing NAND with AND because the distinctive shapes look similar, or replacing ≥1 with & because both are rectangles, is a symbol error, not a Boolean reduction. Replacing a combinational equivalent with a clocked latch because a bubble looks like a storage marker is a category error: inversion is not memory.

When a question shows two drawings and asks whether they are equivalent, write the four-row table for each, or apply one De Morgan pass and cancel double bubbles. If the tables match, the circuits are equivalent regardless of how many packages the original artist used.

Level 2 for B1 and B2 means you can apply these rewrites to a small aircraft discrete network, not merely recite the theorem names. The next section uses the same equivalents to build any function from NAND or NOR alone, and to read landing-gear and warning-lamp schematics.