7.2 Semiconductor Memory Technologies

7.2 Semiconductor Memory Technologies

Topic 5.6(b) is examined at knowledge level 2 for category B2/B2L only. The memory devices, terms, operation, and advantages and limitations taught here come from the former detailed Appendix I description. That former 5.6(a) detail named RAM, ROM and PROM for all licence categories at the levels in section 7.1. This section is the B2 development: how those devices, plus EPROM and EEPROM, actually behave on the address, data and control buses. Categories A, B3 and B1 are not examined on 5.6(b). Software-loading restrictions remain topic 5.13; here the subject is the silicon.

The live Module 5 paper is still three-option multiple-choice, about 75 seconds per question, 75% pass, no negative marking and no essay (B2 72 questions / 90 minutes). OpenExamPrep practice items use four options. This material is independent exam preparation, not an EASA publication.

Memory terms

Fix the vocabulary 5.6(b) expects before naming chemistries.

Address — the unique binary number that selects one location. It is placed on the address bus.

Location (cell) — the storage that holds one word at that address.

Word length (word size) — bits stored at one address and moved on the data bus in one access. It is the second factor in a chip organisation: 8K × 8 means eight-bit words.

Capacity — number of locations times word length. An 8K × 8 device has 8 × 1024 = 8192 locations of 8 bits, which is 65536 bits (64 Kibit), equal to 8 KiB. The K in memory organisations is 1024 (2^10), not 1000. 8K = 2^13, so the chip needs 13 address pins. 2K × 8 needs 11 address pins (2^11 = 2048). 32K × 8 needs 15 address pins (2^15 = 32768).

Access time (t_acc) — delay from a stable address and chip-enable until valid data appear on the data bus for a read. Typical teaching values for older avionics EPROM are 150 ns to 250 ns; SRAM may be tens of nanoseconds.

Cycle time (t_cyc) — minimum time between the start of one access and the start of the next. For SRAM, cycle time is often similar to access time. For DRAM, cycle time is longer because of precharge.

Read cycle / write cycle — a control-bus sequence. Read: address valid, chip-select, output-enable or MEMR, data out. Write: address valid, data valid, chip-select, write strobe.

Random versus sequential access — semiconductor RAM and ROM are random: any address in t_acc. Magnetic tape is sequential.

Volatile versus non-volatile — whether bits survive power removal.

Destructive versus non-destructive readout — classic DRAM readout discharges the storage capacitor and must be followed by a restore write; SRAM and ROM families are non-destructive.

RAM: SRAM and DRAM

Random-access memory is the working store: stacks, variables, input buffers, display refresh maps. The CPU reads and writes it with ordinary load and store cycles. Main limitation: volatility. Remove the supply rail and the bits are gone. Aircraft designs that must keep a scratchpad across a short power interrupt use a keep-alive battery or capacitor, or they reload from non-volatile memory during initialisation.

Static RAM (SRAM) stores each bit in a bistable (typically six transistors). No refresh. Fast. Large cell, so low density and higher cost per bit. Used for small, speed-critical stores: cache, on-chip register files, and modest scratchpads.

Dynamic RAM (DRAM) stores each bit as charge on a capacitor gated by one transistor. Dense and cheap per bit. Capacitors leak, so the device or a controller must refresh every row within a few milliseconds. A missed refresh loses data even though power is present. DRAM readout is historically destructive. Used where a large buffer is needed (older display memories, large data stores). A CPU that outruns DRAM cycle time must honour wait states or use a DRAM controller.

Do not call RAM read-only while power is on — that confuses it with ROM. Do not call SRAM non-volatile because it has no refresh — it still needs continuous power.

ROM, PROM, EPROM, EEPROM and flash

Non-volatile semiconductor stores keep the operational program and constants through a power cycle.

Mask ROM. Patterned at wafer manufacture. Lowest unit cost at high volume. Cannot be changed in service. A software error means a new chip part number and a hardware modification. Fine for truly frozen tables; poor for loadable operational flight programs.

PROM (OTPROM). Shipped blank. A programmer blows fusible links (or equivalent one-time anti-fuses) to write bits. One-time programmable. A single wrong bit and the device is scrap. No quartz window, no electrical erase. Common in older LRUs for firmware that was not expected to change in service.

EPROM (UV-EPROM). Uses floating-gate transistors. Programming injects charge onto the floating gate. Bulk erase by ultraviolet light through a quartz window, typically tens of minutes. Usually the IC must be removed from the board, placed in an eraser, then in a programmer. The window is covered with an opaque label in service so cabin lighting cannot slowly erase it. You cannot erase a single byte. Older avionics OFPs were often UV-EPROM.

EEPROM. Electrically erasable PROM. Programming and erase use electrical pulses. Byte or page erase/write is possible in circuit. Writes are slower than reads. Write endurance is finite: industry teaching places it on the order of 10^4 to 10^6 cycles per location, device-dependent — that range is not an EASA-published constant. Used for configuration parameters, small data logs, and some firmware.

Flash memory. A block-oriented EEPROM variant. Erase is by sector or block, not typically by single byte. High density. This is the usual store for modern loadable operational programs. Data loading, integrity checks and the prohibition on unapproved software changes are topic 5.13; the device physics belong here. Flash still has endurance limits and must not be treated as infinite-write RAM.

Typical memory operation on the buses

A read cycle:

1. The CPU places the address on the address bus and holds it.
2. The decoder asserts chip-select for one device.
3. The control bus asserts memory-read (or R/W = read and output-enable).
4. After t_acc, the device drives the data bus. The CPU latches the word into the memory-data register.
5. Chip-select and read are de-asserted; the device returns to high-impedance.

A write cycle (RAM, or EEPROM/flash under a programming sequence):

1. Address valid, chip-select asserted.
2. The CPU drives data onto the data bus.
3. The write strobe latches the bits into the selected location.
4. The buses are released.

If t_acc is longer than the CPU's natural memory cycle, the memory (or wait-state logic) pulls READY false and the CPU inserts wait states until data are valid.

Worked organisation and wait-state example

Chip marked as an 8K × 8 UV-EPROM:

• Locations: 8 × 1024 = 8192.
• Address pins: 13, because 2^13 = 8192.
• Data pins: 8.
• Capacity: 8192 × 8 = 65536 bits = 8 KiB.
• Non-volatile; read-only in the aircraft unless removed, UV-erased and reprogrammed.
• If the CPU data bus is 16 bits, two such chips can be paralleled as an 8K × 16 pair (even/odd byte), doubling word length without doubling address bits.

Access-time arithmetic: CPU clock 10 MHz so one T-state is 100 ns. EPROM t_acc = 150 ns. A 100 ns memory cycle is shorter than 150 ns, so at least one wait state (another 100 ns) must be added or the CPU will latch the data bus while the PROM outputs are still invalid. Fitting a slow PROM on a fast CPU without wait-state strapping causes intermittent, address-dependent faults that look like bad software.

A 32K × 8 SRAM in the same map needs 15 address bits (2^15 = 32768) and is volatile. Mixing the two organisations — treating 8K as eight address bits, or treating the × 8 as 8K — is the usual arithmetic trap.

Advantages and limitations of storage systems

The former detailed Appendix I description asked for advantages and limitations, not brand names.

Semiconductor RAM — advantage: read and write at electronic speed, random access, simple CPU interface. Limitation: volatility; DRAM refresh; SRAM cost and density.

Semiconductor ROM / PROM / EPROM / EEPROM / flash — advantage: non-volatility, random access, no moving parts, suitable as an airborne instruction store. Limitations: mask ROM and PROM cannot be updated (or only once); UV-EPROM erase is slow and usually off-board; EEPROM and flash writes are slow and endurance-limited; unauthorised rewrite of flight software is an airworthiness event (topic 5.13).

Magnetic rotating disk — huge capacity, non-volatile. Limitations: moving parts, vibration and altitude, slow seek. Not used as the primary flight-control program store.

Magnetic tape and other sequential stores — cheap archive. Limitation: no random access; long latency. Not a real-time instruction store.

Optical disc — a ground distribution medium, not a flight-control execution store.

For Module 5 the operational choice is: execute from non-volatile ROM-family devices; compute in RAM; preserve configuration in EEPROM or flash under controlled loading. Section 7.3 then shows how the microprocessor fetches an instruction from that ROM-family store.