8.1 Integrated Circuit Technology, Encoders, Decoders and Scale of Integration

8.1 Integrated Circuit Technology, Encoders, Decoders and Scale of Integration

Commission Implementing Regulation (EU) 2023/989 lists Module 5.8, Integrated circuits, as a Category B2/B2L knowledge-level-2 topic. Encoders, decoders, and the MSI/LSI/VLSI scale of integration come from the pre-12 June 2024 detailed Appendix I description and are retained as historical study scope. Categories A, B3 and B1 are not examined on 5.8, yet the same packages sit on almost every electronic instrument card. This section builds the B2 picture: how many gates live on one die, how an encoder differs from a decoder, why a priority encoder is used when two discretes can be true at once, how a BCD-to-7-segment decoder drives a numeric window, and how TTL and CMOS families behave on a typical 5 V avionics rail.

What an integrated circuit is on an aircraft card

An integrated circuit (IC) is a complete electronic function fabricated on a single semiconductor die — almost always silicon — and sealed in a dual-in-line, small-outline, flat-pack or ceramic package. The die is bonded to a lead frame; the pins that leave the package are the only nodes a line technician can probe. Typical pins are VCC (or VDD), ground (GND or VSS), data inputs, data outputs, and one or more enable or strobe pins that are often active-low. Markings such as 74LS138, 74HC148 or CD4511B identify the logic family and the function. Because internal nodes are inaccessible, troubleshooting is package-oriented: confirm supplies and enables, then substitute a known-good device of the same family and speed grade.

Scale of integration: SSI, MSI, LSI and VLSI

Scale of integration is a count of equivalent two-input gates, or of transistors, on one die. Part-66 teaching uses four historical bands. Small-scale integration (SSI) holds fewer than about twelve gates: the 7400 quad NAND, 7404 hex inverter, 7408 quad AND and 7432 quad OR are SSI. Medium-scale integration (MSI) holds roughly twelve to ninety-nine gates and is the home of the devices named in topics 5.8 and 5.9: the 74138 3-to-8 decoder, 74148 8-to-3 priority encoder, 74151 8-to-1 multiplexer and 7447 BCD-to-7-segment decoder. Large-scale integration (LSI) covers about one hundred to ten thousand gates: early UART/USART channels, modest memory arrays and simple microcontroller cores. Very-large-scale integration (VLSI) exceeds about ten thousand gates and, on modern aircraft, millions of transistors: cockpit display processors, AFDX end-systems, and the core processors inside an Integrated Modular Avionics cabinet.

A useful maintenance rule follows the scale. An SSI failure often looks like a single gate stuck high or low. An MSI failure takes a whole function — every chip-select from a 74138, or every segment of one digit — in one package. LSI and VLSI failures are board- or module-level events; you do not repair the die. The examination trap is to treat MSI, LSI or VLSI as a manufacturer’s brand. They are density classes, not part numbers. A 74138 is MSI whether it was made by Texas Instruments, National or a later CMOS second source.

Encoders versus decoders

An encoder compresses many mutually exclusive input lines into a shorter binary word. A decoder expands a binary word into many mutually exclusive output lines. They are inverse combinational blocks:

• Encoder: 2^n data inputs produce n binary outputs (examples: 8-to-3, 16-to-4, decimal-to-BCD).
• Decoder: n binary inputs produce 2^n data outputs (examples: 2-to-4, 3-to-8, 4-to-16, BCD-to-decimal).

A decimal-to-BCD encoder has ten push-button or discrete inputs (digits 0–9) and four BCD outputs weighted 8-4-2-1. A BCD-to-decimal decoder has four BCD inputs and ten mutually exclusive outputs, one per digit. On logic diagrams the encoder is often a trapezoid with the wide side as inputs and the narrow side as the binary code; the decoder is the opposite trapezoid, or a rectangle labelled BIN/OCT, 3–8 or BCD/DEC. IEC-style boxes may simply read ENC or DEC with binary weights on the code pins.

Worked identification. An 8-to-3 encoder has inputs I0–I7 and outputs A2, A1, A0. If only I5 is asserted, the binary code is 101, so A2 = 1, A1 = 0, A0 = 1. If I5 and I2 were both asserted on a simple (non-priority) encoder, the two codes 101 and 010 would be OR-ed into 111 — a false indication of input 7. That is why panel-switch and discrete-scan circuits on aircraft use a priority encoder rather than a plain encoder.

A decoder example sits on almost every memory-mapped avionics card. A 74138 accepts a 3-bit address A2 A1 A0 plus two or three enable pins (typically G1 high and G2A/G2B low). Only one of Y0–Y7 goes low, selecting one device. If the enables are wrong, every output stays inactive: the classic fault in which a whole memory or I/O block looks dead because chip-select never fires. The 74154 4-to-16 decoder extends the same idea to sixteen outputs.

Priority encoder

A priority encoder still maps 2^n inputs onto n outputs, but every input has a fixed rank. When several inputs are true, only the highest-priority input is encoded. The 74LS148 is the textbook 8-line to 3-line priority encoder. Input 7 outranks 6, which outranks 5, and so on down to 0. Enable-in (EI) must be low for the device to encode; group-select (GS) and enable-out (EO) cascade two packages into a 16-to-4 encoder without extra SSI gates. If I7 and I2 are both active, the 74148 outputs the code for 7, not 2 and not the OR of the two codes. Keyboard matrices, audio-selecting panels and discrete-warning concentrators use that behaviour so a two-switch press reports the higher-priority discrete instead of a corrupt mixture.

The 74147 is a 10-line to 4-line BCD priority encoder: nine active-low inputs encode digits 1–9; digit 0 is implied when none of 1–9 is pressed. Active-low inputs are drawn with bubbles on the logic symbol; missing the bubble is a common schematic-reading error and will invert your idea of which switch is closed.

BCD-to-7-segment decoder as the typical MSI application

Numeric windows — radio frequency, radio altitude, flap position on older panels — often use seven-segment LED or filament displays. Seven segments a–g must be driven in a unique pattern for each decimal digit. A BCD-to-7-segment decoder/driver such as the 7447 (open-collector, active-low, intended for common-anode LEDs) or 7448 (active-high) accepts a 4-bit BCD nibble and produces those seven drives. Digit 8 lights every segment; digit 1 lights only b and c. Invalid BCD codes 1010–1111 blank the digit or show a non-decimal glyph, depending on the device. Worked BCD: decimal 6 is 0110 (weights 8-4-2-1), which the decoder turns into the segment pattern for 6.

Two extra pins matter in service. Lamp-test (LT) forces every segment on so a bulb or LED check can be done from a master-test switch — the same operating idea as a flight-deck instrument test. Ripple-blanking input and output (RBI/RBO) suppress leading zeros so a four-digit radio-altimeter window shows 350 rather than 0350. On a diagram you identify the function even without a trapezoid: four BCD pins weighted 8-4-2-1, seven segment pins a–g, and LT/BI/RBO.

A decoder is not automatically a high-current driver. Large LEDs, 28 V lamps and sunlight-readable displays still need transistors or a dedicated driver between the decoder and the load. Treating the 7447 as a complete 28 V lamp driver is a practical and examination error. The CMOS CD4511B is the 4000-series BCD-to-7-segment latch/decoder/driver used on many later cards: it latches the BCD, which stops the display from flickering while the bus is multiplexed.

TTL versus CMOS, briefly

Two families dominate legacy digital avionics. Transistor–transistor logic (TTL: 74, 74LS, 74S, 74F) uses bipolar NPN structures. The standard supply is 5 V. Typical levels are VOH ≥ 2.4 V, VOL ≤ 0.4 V, VIH ≥ 2.0 V, VIL ≤ 0.8 V. TTL is relatively fast and has defined fan-out into other TTL inputs, but it draws milliamps of static supply current even when idle, so local decoupling capacitors are mandatory. Totem-pole outputs must not be tied together; open-collector types may be wire-ANDed with a pull-up.

Complementary MOS (CMOS: 4000-series, 74HC, 74HCT, 74AC) uses enhancement MOSFETs. Static supply current is near zero; outputs swing rail-to-rail; 4000-series parts tolerate a wide supply, often 3 V to 15 V. 74HCT is CMOS that accepts TTL input thresholds, which is the intended way to mix a 74LS output into a CMOS input on a 5 V board. CMOS inputs must never float: unused inputs are tied to VCC or ground, otherwise the gate can oscillate and overheat. CMOS is far more electrostatic-sensitive than TTL, which is why Module 5.12 handling rules matter as soon as you unseat these packages. Do not casually replace a 74LS device with a 4000-series CMOS device: supply voltage, speed, output drive and input thresholds all differ. 74HC may replace 74LS where 5 V levels and timing allow; 74HCT is the safer TTL-compatible CMOS substitute.

Reading the function on a wiring diagram

Identify encoders and decoders by function names (ENC, PRIORITY ENC, DEC, BCD-7SEG), binary weights (A0–A3 or 1-2-4-8), enable bubbles, and cascade pins EI/EO or RBI/RBO. A failed MSI decoder on a memory map typically kills an entire block of chip-selects at once — that pattern is how you distinguish an MSI fault from a single SSI gate.