11.3 Multivibrators & Timing Circuits

11.3 Multivibrators & Memory

Quick Answer: Astable = two unstable states (free-running square-wave clock). Monostable = one-shot: flips briefly, returns after a set time. Bistable = flip-flop (two stable states); used to divide frequency. Astable CE collectors → square wave. RAM = read/write random access; ROM = fixed pattern; DRAM needs refresh. Volatile loses data without power; nonvolatile keeps it.

Key topic 037 classifies multivibrators by how many stable states they have. Key topic 038 names the memory chips that store the bits those circuits create. Together they explain both the free-running clock crystal’s digital sidekick and the firmware that boots a modern transceiver.

Multivibrators — three families

A multivibrator is a regenerative two-state switching circuit. The “multi” is historical; what matters on Element 3 is astable / monostable / bistable.

Astable multivibrator

What is an astable multivibrator? A circuit that alternates between two unstable states.

No external clock is required—the circuit is its own oscillator. Two amplifier stages with RC cross-coupling (classic transistor pair or a 555-style topology) never rest; each state times out and flips the other.

What waveform appears on the voltage outputs at the collectors of an astable multivibrator common-emitter stage? A square wave.

Collectors slam between near-cutoff and near-saturation, so the waveform is rectangular/square, not sine, sawtooth, or half-wave pulses. That square wave is a natural logic clock or a tone for testing digital stages.

Monostable multivibrator (one-shot)

What is a monostable multivibrator? A circuit that can be switched momentarily to the opposite binary state and then returns after a set time to its original state.

One state is stable; the other is temporary. A trigger pulse starts the timing interval (RC network or digital timer); when the interval ends, the circuit snaps back. Uses on radio gear:

• Stretch a short PTT contact bounce into a clean keying pulse.
• Generate a fixed-width mute blanking interval after channel change.
• Produce a single enable pulse for a DAC update or synthesizer load strobe.

Do not confuse monostable with a free-running clock (that is astable) or with a permanent bit store (that is bistable).

Bistable multivibrator = flip-flop

What is a bistable multivibrator circuit commonly named? A flip-flop.

What is a bistable multivibrator circuit? A flip-flop.

Two stable states → holds 0 or 1 until set, reset, or clocked. This is the same device family as §11.2, now named from the multivibrator taxonomy.

The frequency of an AC signal can be divided electronically by what type of digital circuit? A bistable multivibrator.

Each toggle stage halves frequency. Free-running (astable) multivibrators generate a frequency; they do not systematically divide an external AC signal the way cascaded flip-flops do. OR gates are combinational and do not count. That is why the pool answer is bistable, not astable or free-running.

Multivibrator decision tree for the exam

Semiconductor memory — RAM, ROM, DRAM

RAM — random-access memory

Name of the semiconductor memory IC whose digital data can be written or read, and whose memory word address can be accessed randomly: RAM – Random-Access Memory.

“Random access” means any address is available in roughly the same time—unlike sequential tape. Working variables, channel scratchpads, and packet buffers live in RAM while power is on.

ROM — read-only memory

Name of the semiconductor IC that has a fixed pattern of digital data stored in its memory matrix: ROM – Read-Only Memory.

Factory-masked or permanently programmed content: boot code, fixed lookup tables, character generators. You read it; you do not casually rewrite it in the field (contrast EEPROM/flash below).

DRAM — dynamic RAM needs refresh

Name of the random-accessed semiconductor memory IC that must be refreshed periodically to maintain reliable data storage: DRAM – Dynamic Random-Access Memory.

DRAM stores bits as charge on tiny capacitors. Charge leaks; a refresh controller rewrites cells before data vanishes. SRAM (static RAM) uses flip-flop cells and does not need refresh, but costs more silicon per bit—Element 3 explicitly tests the DRAM + refresh pair.

Memory cell count (address × data width)

How many individual memory cells in a memory IC with 4 data bus I/O pins and 4 address pins? 64.

Reasoning:

• 4 address pins select (2^4 = 16) addresses.
• 4 data pins mean 4 bits per address.
• Total cells = (16 \times 4 = 64).

General rule: cells ≈ (2^{address pins}) × (data width in bits) for a simple parallel memory organization.

IO and program (system vocabulary from the pool)

What does “IO” mean within a microprocessor system? Input-output.

What is the name for a microprocessor’s sequence of commands and instructions? A program.

IO is how the CPU talks to keypads, displays, synthesizer chips, and AF stages. The program is the ordered instruction stream—usually fetched from ROM/flash into the execution path, with RAM holding temporary data.

EPROM, EEPROM, and flash (nonvolatile context)

The numbered pool names EPROM mainly as a distractor in RAM questions, but GROL fieldwork requires the family distinctions:

Volatile vs nonvolatile:

• Volatile (RAM/DRAM): data vanishes when power is removed—working memory, volatile channel scratchpads without battery backup.
• Nonvolatile (ROM/EPROM/EEPROM/flash): firmware, calibration constants, and saved channel banks survive power-off.

Modern radios store firmware in flash, user preferences in EEPROM or flash file systems, and live DSP buffers in RAM/DRAM. Battery-backed SRAM still appears in older avionics for configuration.

Shop story — dead after power cycle

Symptoms: radio works until battery disconnect, then boots to defaults or “no program.”

1. Check whether configuration was only in volatile RAM without backup.
2. Verify flash/EEPROM still has firmware (nonvolatile failure is rarer but catastrophic).
3. Distinguish “lost user channels” (EEPROM/config) from “won’t boot” (ROM/flash corruption).

Exam-day checklist for 037–038

1. Astable → two unstable states; collectors → square wave.
2. Monostable → momentary flip, returns after set time.
3. Bistable → flip-flop; divides frequency.
4. RAM → read/write random access; ROM → fixed pattern.
5. DRAM → must be refreshed.
6. 4 address + 4 data pins → 64 cells.
7. IO = input-output; instruction sequence = program.
8. Volatile loses data without power; ROM/EPROM/EEPROM/flash keep it.

Next section puts memory and clocks inside microprocessors, then covers counters, prescalers, BCD, ADC, and DAC—the digital heart of frequency synthesis and modern radio signal chains.