11.2 Flip-Flops & Sequential Elements

11.2 Logic Levels & Flip-Flops

Quick Answer: TTL = transistor-transistor logic, usually on 5 V. Valid TTL input low ≈ 0–0.8 V; valid high ≈ 2.0–5.5 V. Open TTL inputs float high. Best checker: logic probe. A flip-flop has 2 stable states and stores 1 bit. 2 flip-flops divide frequency by 4; 8 R-S flip-flops make an 8-bit register. R-S does not toggle with R-S held constant under clock.

Gates alone are combinational—outputs follow inputs immediately. Real radios need memory and predictable voltage bands. Key topic 033 locks in TTL numbers; key topic 036 introduces the flip-flop as the one-bit memory cell.

TTL — transistor-transistor logic

What do the initials TTL stand for? Transistor-transistor logic.

TTL is the classic bipolar digital family (7400-series and descendants). Internally, multi-emitter bipolar transistors form the input structure—hence the name, not “resistor-transistor,” “diode-transistor,” or “emitter-coupled” logic (those are other historical families: RTL, DTL, ECL).

Power supply

Common power supply voltage for TTL series integrated circuits: 5 volts.

Ship and aircraft 12/24/28 V buses always step down (regulators, DC-DC converters) before feeding TTL. Never assume a bare chassis voltage is safe for a TTL package—look for the +5 V logic rail and its ground return.

Valid logic levels (5 V TTL)

Valid logic low input in a TTL device operating at 5 volts: zero to 0.8 volts.

Valid logic high input in a TTL device operating at 5.0 volts: 2.0 to 5.5 volts.

The gap between 0.8 V and 2.0 V is the undefined / transition region. A noisy signal stuck at 1.4 V is not a legal 0 or 1—expect flaky gates, oscillation, or excess supply current. That gap is also where noise margin lives: the difference between a guaranteed output high/low and the worst-case input threshold that still reads correctly.

Noise margin (technician view)

Noise margin is how much interference a logic input can tolerate before a legal 0 looks like a 1 (or vice versa).

TTL’s wide gap (0.8 V low max vs 2.0 V high min) gives solid margins for short board runs. Long cable runs, shared grounds with RF decks, and weak pull-ups erode that margin—exactly when radios get “ghost” key-ups and intermittent synthesizer unlocks.

Open TTL inputs

TTL inputs left open develop what logic state? A high-logic state.

Floating TTL inputs are not “ignored” and are not random by design—they tend to rise toward a high because of internal structure. That high can make an unused AND input look permanently true, or turn a NOR into a stuck-low output. Good practice: tie unused inputs to a defined level (often high via resistor for TTL, or per datasheet for CMOS).

Best instrument for TTL checks

Which instrument is best for checking a TTL logic circuit? A logic probe.

A logic probe is designed for digital high/low/pulse indication at TTL (and often CMOS) thresholds. A general VOM/DMM can measure voltage but is slow for pulsing nets and does not give an instant “high / low / pulse” indication. Continuity testers are for wiring, not live logic states.

CMOS levels (comparison for modern radios)

Element 3’s numbered pool emphasizes TTL thresholds, but modern marine/aviation radios are full of CMOS (complementary metal-oxide semiconductor) microcontrollers and synthesizer logic. CMOS often runs at 5 V, 3.3 V, or lower, and its valid high/low fractions track a larger portion of VCC than classic TTL.

When you interface a legacy TTL board to a CMOS MCU on a retrofit, use level translators or series resistors per the datasheet—do not assume 5 V high is safe on a 3.3 V pin.

Flip-flops — two stable states, one bit

A flip-flop circuit is a binary logic element with how many stable states? 2.

What is a flip-flop circuit? A binary sequential logic element with 2 stable states.

Those two states are logic 0 and logic 1 at the Q output (with (\overline{Q}) complementary on many packages). Unlike an AND gate that forgets inputs the instant they change, a flip-flop remembers until something commands a change—set, reset, clocked data, or toggle.

How many bits of information can be stored in a single flip-flop circuit? 1.

Registers, shift registers, and counters are just arrays of flip-flops sharing clocks and control lines.

Latches vs flip-flops (field distinction)

Element 3 wording centers on “flip-flop” and R-S behavior; in the shop, treat edge-triggered parts as the reliable choice for clocked radio logic so data is not still changing while the enable is open.

R-S (SR) flip-flop

R = Reset, S = Set (sometimes labeled R/S or (\overline{R})/(\overline{S}) for active-low).

Many packages add asynchronous PRE (preset) and CLR (clear) that force Q without waiting for the clock, and synchronous R-S (or D) inputs sampled when CLK is initiated.

How many R-S flip-flops are required to construct an 8-bit storage register? 8 — one flip-flop per bit.

An R-S flip-flop is capable of doing all of the following except: operate in toggle mode with R-S inputs held constant and CLK initiated.

That “except” is a classic pool trap. R-S can:

• Accept data into R-S with CLK initiated (synchronous path).
• Accept PRE/CLR without CLK (asynchronous path).
• Refuse synchronous data when asynchronous inputs are asserting (async wins).

It does not free-run as a toggle just because the clock keeps ticking while R and S sit fixed. Toggle mode is the T flip-flop (or a JK wired for toggle).

D, JK, and T (technician map)

Frequency division with flip-flops

Each toggle stage halves frequency: (f_{out} = f_{in}/2).

How many flip-flops are required to divide a signal frequency by 4? 2.

[ \frac{f}{2} \xrightarrow{\text{1st FF}} \frac{f}{4} \xrightarrow{\text{2nd FF}} ]

Chain more stages for ÷8, ÷16, and so on—exactly how binary counters and many PLL reference dividers are built (expanded in §11.4).

Worked example — 8-bit channel latch

A legacy marine VHF control board latches an 8-bit channel code from a rotary encoder:

1. Eight D or R-S flip-flops share one clock derived from the encoder “enter” pulse.
2. Each flip-flop stores one bit of the channel number (8 bits → 8 flip-flops).
3. Q outputs feed the synthesizer programming lines until the next enter pulse.
4. If one flip-flop fails stuck, one bit of the channel is frozen—symptoms look like “wrong frequency but panel display correct” when the display is driven from a different path.

TTL probing checklist on a live radio

1. Confirm +5 V rail and clean ground at the IC before blaming logic.
2. Use a logic probe for high/low/pulse on TTL pins.
3. Treat 0–0.8 V as low, 2.0–5.5 V as high; distrust mid-band voltages.
4. Do not leave unused TTL inputs floating—they read high.
5. Remember flip-flops hold state after power glitches if the supply stayed up—cycle power when stuck bits make no sense.

Exam-day checklist for 033 & 036

1. TTL = transistor-transistor logic; supply 5 V.
2. Low input 0–0.8 V; high input 2.0–5.5 V.
3. Open TTL input → high; best tool → logic probe.
4. Flip-flop → 2 stable states; stores 1 bit.
5. ÷4 needs 2 flip-flops; 8-bit register needs 8 R-S flip-flops.
6. R-S does not toggle with R-S constant under clock.

Next section folds flip-flops into the multivibrator family and compares RAM/ROM memory types that hold programs and channel data in radio gear.