11.1 Logic Gates & Boolean Functions

11.1 Logic Types & Gates

Quick Answer: Positive logic: 1 = high, 0 = low. Negative logic: 0 = high, 1 = low. AND → 1 only if all inputs are 1. OR → 1 if any input is 1. NOT inverts. NAND → 0 only when all inputs are 1. NOR → 0 if any/all inputs are 1. XOR → 1 when inputs differ. A truth table lists every input combination and its output.

Topic 3-E (Digital Logic) is eight key topics on the Element 3 blueprint—one exam item drawn from this family on a typical 100-question paper. Key topics 034 (Logic Gates) and the positive/negative-logic half of 035 (Logic Levels) are pure gate literacy. Master them once and every later counter, flip-flop, and microprocessor question rests on the same HIGH/LOW vocabulary.

Positive logic vs negative logic

Digital circuits deal in two voltage bands. What those bands mean as Boolean values depends on the logic convention of the schematic or IC family.

In a positive-logic circuit, what level is used to represent a logic 1? High level.

In a negative-logic circuit, what level is used to represent a logic 0? High level.

Negative logic feels backward at first, but it is still two-valued Boolean algebra—only the voltage-to-meaning map is inverted. Active-low chip selects, open-collector bus lines, and “asserted low” control signals on radio backplanes often behave like negative-logic statements even when the surrounding board is drawn with positive-logic symbols. Always read the schematic note: active high versus active low.

Why GROL techs care

A marine DSC controller may light a fault LED when an active-low /FAULT pin goes low. If you assume positive-logic “high means alarm,” you will chase the wrong rail. The same pin labeled with a bar (\overline{FAULT}) or slash (/FAULT) is the schematic’s way of saying “asserted when low.”

What a truth table is

What is a truth table? A list of input combinations and their corresponding outputs that characterizes a digital device’s function.

It is not a table of op-amp symbols, and it is not merely a diagram of “when the output is true.” For an n-input gate there are (2^n) rows. Two-input gates have four rows; three-input gates have eight. Element 3 figures (pool Figures 3E12–3E14 style) chain gates and ask you to walk voltages from left to right—exactly what a truth table trains you to do.

The six gates you must own

Assume positive logic and two inputs A and B unless noted. Output is Y.

AND

Characteristic of an AND gate: produces a logic “1” at its output only if all inputs are logic “1”.

Which gate provides an active high out when both inputs are active high? AND.

Boolean: (Y = A \cdot B) or (Y = AB). Everyday radio use: enable a transmit path only when PTT is true AND channel is unlocked AND power is good.

OR

Characteristic of an OR gate: produces a logic “1” at its output if any input is logic “1”.

Boolean: (Y = A + B). Use case: raise an alarm if over-temp OR VSWR fault OR supply undervoltage.

NOT (inverter)

Characteristic of a NOT gate: produces a logic “0” at its output when the input is logic “1” and vice versa.

Boolean: (Y = \overline{A}). Single-input only. Bubble on a schematic input or output is the NOT symbol. Inverters clean up weak levels, create complementary clocks, and flip active-high controls to active-low.

NAND (NOT-AND)

Characteristic of a NAND gate: produces a logic “0” at its output only when all inputs are logic “1”.

NAND is the universal gate: any Boolean function can be built from NANDs alone. That is why classic TTL catalogs stocked 7400 NAND quads by the million, and why Element 3 schematic figures love NAND chains.

NOR (NOT-OR)

Characteristic of a NOR gate: produces a logic “0” at its output if any or all inputs are logic “1”.

NOR is also universal. Output is 1 only when every input is 0—the dual of NAND’s “0 only when every input is 1.”

XOR (exclusive OR)

Characteristic (pool and practice banks): XOR produces a HIGH only when its two inputs differ (one high, one low). Same inputs → low.

Boolean: (Y = A\overline{B} + \overline{A}B). Radio uses: parity generation, phase detectors in simple digital PLLs, comparing two bit streams for “equal / not equal,” and modulo-2 adders in scramblers.

Gate summary card

Boolean basics for the bench

Element 3 does not demand full Boolean algebra proofs, but you need the operators and simplification habits:

Identity shortcuts (exam-useful):

• (A \cdot 1 = A), (A \cdot 0 = 0)
• (A + 0 = A), (A + 1 = 1)
• (A \cdot A = A), (A + A = A)
• (A \cdot \overline{A} = 0), (A + \overline{A} = 1)
• Double inversion: (\overline{\overline{A}} = A)

DeMorgan’s theorems (overview)

DeMorgan converts between AND/OR forms under inversion:

[ \overline{A \cdot B} = \overline{A} + \overline{B} ]

[ \overline{A + B} = \overline{A} \cdot \overline{B} ]

In words:

1. NAND of inputs = OR of inverted inputs.
2. NOR of inputs = AND of inverted inputs.

Bench meaning: a board full of NAND packages can implement an OR of inverted signals by wiring inverted (bubbled) inputs into a NAND—exactly how many control PLD replacements and discrete glue-logic repairs are done when a part is obsolete. When an exam figure shows NANDs with bubbles, rewrite the function with DeMorgan before guessing the truth-table row.

Worked rewrite

Suppose a transmit-enable needs “RF is good OR bypass is selected,” but you only have NAND chips:

• Desired: (Y = G + B)
• DeMorgan: (Y = \overline{\overline{G} \cdot \overline{B}}) — invert G and B, NAND them, done.

Walking multi-gate figures (pool skill)

Key topic 035 includes multi-gate figures (3E12–3E14 style). Method:

1. Assume positive logic unless told otherwise.
2. Label every known L/H at the left inputs.
3. Evaluate the first gate from its truth table; write the result on its output net.
4. Feed that net into the next gate; continue to the labeled test points.
5. NAND is the usual symbol on those figures—remember NAND is 0 only when both inputs are 1.

Example (conceptual NAND chain): if both inputs to a first NAND are high, its output is low. That low into a second NAND forces the second output high (because not all inputs are high). Trace slowly; speed comes from muscle memory, not panic.

Boolean to radio control — shop examples

Exam-day checklist for gates & logic types

1. Positive logic: 1 = high; negative logic: 0 = high.
2. Truth table = all input combos → outputs that define the device.
3. AND: 1 only if all 1; active-high-and-active-high → AND.
4. OR: 1 if any 1.
5. NOT: invert.
6. NAND: 0 only if all 1; NOR: 0 if any 1.
7. XOR: 1 when inputs differ.
8. DeMorgan: flip AND↔OR and invert each literal under a bar.

Nail this section and Element 3 digital questions stop looking like abstract computer science—they become the same interlock logic you already troubleshoot on a radio chassis. Next: TTL/CMOS voltage bands and flip-flops that remember a bit.