9.4 Boolean Algebra, Logic Gates, De Morgan's Laws & Ladder Logic Control Diagrams

9.4 Boolean Algebra, Logic Gates, De Morgan's Laws & Ladder Logic Control Diagrams

Executive Overview: Industrial control systems, automated motor control centers (MCCs), protective relay tripping matrices, and Programmable Logic Controllers (PLCs) operate on fundamental principles of Boolean algebra and ladder logic. The NCEES PE Power exam tests candidate mastery of logic gate simplification, De Morgan's duality laws, Karnaugh map minimization, and the translation of control schematics into ladder logic rungs. A thorough understanding of fail-safe contact wiring (Normally Open vs. Normally Closed) and interlocking circuitry is essential for scoring full marks on control domain questions.

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1. Boolean Algebra Laws & Axioms

Boolean algebra operates on binary variables restricted to two distinct states: $\mathbf{0}$ (False, Low, De-energized, $0\text{ V}$) and $\mathbf{1}$ (True, High, Energized, $24\text{ VDC} / 120\text{ VAC}$). The three fundamental operators are:

1. Conjunction (AND): $A \cdot B$ or $AB$ (Output is $1$ only if both $A=1$ and $B=1$).
2. Disjunction (OR): $A + B$ (Output is $1$ if $A=1$ or $B=1$ or both).
3. Negation (NOT / Complement): $\overline{A}$ or $A'$ (Inverts $0 \to 1$ and $1 \to 0$).

+-----------------------------------------------------------------------------------------+
|                         BOOLEAN ALGEBRA THEOREM CHEAT SHEET                             |
+---------------------+-------------------------------+-----------------------------------+
| Theorem Name        | AND Form (Conjunction)        | OR Form (Disjunction)             |
+---------------------+-------------------------------+-----------------------------------+
| **Identity**        | A * 1 = A                     | A + 0 = A                         |
| **Null (Dominance)**| A * 0 = 0                     | A + 1 = 1                         |
| **Idempotence**     | A * A = A                     | A + A = A                         |
| **Complement**      | A * A' = 0                    | A + A' = 1                        |
| **Involution**      | (A')' = A                     | --                                |
| **Commutative**     | A * B = B * A                 | A + B = B + A                     |
| **Associative**     | A * (B * C) = (A * B) * C     | A + (B + C) = (A + B) + C         |
| **Distributive**    | A * (B + C) = A*B + A*C       | A + (B * C) = (A + B) * (A + C)   |
| **Absorption**      | A * (A + B) = A               | A + A*B = A                       |
| **Elimination**     | A * (A' + B) = A * B          | A + A'*B = A + B                  |
+---------------------+-------------------------------+-----------------------------------+

High-Yield Exam Identity: The second distributive law, $A + BC = (A + B)(A + C)$, and the elimination law, $A + \overline{A}B = A + B$, frequently appear on PE exam questions to rapidly reduce expressions without long truth table derivations.

De Morgan's Laws

De Morgan's laws state that the complement of a product equals the sum of the complements, and the complement of a sum equals the product of the complements:

$\overline{A \cdot B} = \overline{A} + \overline{B}$ $\overline{A + B} = \overline{A} \cdot \overline{B}$

Generalized De Morgan Formulation

$\overline{A_1 \cdot A_2 \cdot A_3 \dots A_n} = \overline{A_1} + \overline{A_2} + \overline{A_3} \dots + \overline{A_n}$ $\overline{A_1 + A_2 + A_3 \dots + A_n} = \overline{A_1} \cdot \overline{A_2} \cdot \overline{A_3} \dots \cdot \overline{A_n}$

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2. Logic Gates & Universal Gate Implementation

+-----------------------------------------------------------------------------------------+
|                                STANDARD LOGIC GATE SUMMARY                              |
+------------+-----------------------+-------------------------+--------------------------+
| Gate Name  | Logic Symbol          | Boolean Expression      | Truth Table Function     |
+------------+-----------------------+-------------------------+--------------------------+
| **AND**    | Standard D-shape      | F = A * B               | 1 only when all inputs 1 |
| **OR**     | Curved shield shape   | F = A + B               | 1 when any input is 1    |
| **NOT**    | Triangle with bubble  | F = A'                  | Inverts input state      |
| **NAND**   | AND with bubble       | F = (A * B)'            | 0 only when all inputs 1 |
| **NOR**    | OR with bubble        | F = (A + B)'            | 1 only when all inputs 0 |
| **XOR**    | Double-curved OR      | F = A (+) B = A'B + AB' | 1 when inputs differ     |
| **XNOR**   | XOR with bubble       | F = (A (+) B)' = AB+A'B'| 1 when inputs are equal  |
+------------+-----------------------+-------------------------+--------------------------+

Universal Gates (NAND & NOR)

Both NAND and NOR are universal gates; any arbitrary Boolean logic function can be constructed using exclusively NAND gates or exclusively NOR gates:

• NOT from NAND: $\overline{A} = \overline{A \cdot A}$
• AND from NAND: $A \cdot B = \overline{\overline{A \cdot B}}$ (NAND followed by NAND inverter)
• OR from NAND: $A + B = \overline{\overline{A} \cdot \overline{B}}$ (Invert inputs, then NAND)

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3. Karnaugh Map (K-Map) Minimization

K-maps provide a visual, systematic technique to simplify Boolean expressions into minimal Sum-of-Products (SOP) or Product-of-Sums (POS) forms without algebraic trial and error.

Gray Code Coordinate Ordering

K-map rows and columns must be ordered using Gray Code ($00, 01, 11, 10$) so that adjacent cells differ by exactly one binary variable. Adjacency wraps around the boundaries (the top row is adjacent to the bottom row; the leftmost column is adjacent to the rightmost column).

               3-Variable K-Map (Variables A, B, C) where rows = A, cols = BC

                       BC = 00      BC = 01      BC = 11      BC = 10
                   +------------+------------+------------+------------+
            A = 0  |  m_0 (000) |  m_1 (001) |  m_3 (011) |  m_2 (010) |
                   +------------+------------+------------+------------+
            A = 1  |  m_4 (100) |  m_5 (101) |  m_7 (111) |  m_6 (110) |
                   +------------+------------+------------+------------+

K-Map Grouping Rules

1. Groups of cells containing $\mathbf{1}$s must be rectangular and contain a power of 2 number of cells ($1, 2, 4, 8, 16$).
2. Make groups as large as possible to eliminate the maximum number of literal variables (a group of 2 eliminates 1 variable; a group of 4 eliminates 2 variables; a group of 8 eliminates 3 variables).
3. Groups may overlap to include minterms in multiple groups.
4. Prime Implicants (PI): A maximal group of $1$s that cannot be combined with any other group.
5. Essential Prime Implicants (EPI): A prime implicant that covers at least one minterm ($1$) not covered by any other prime implicant. All EPIs must be included in the final minimal expression.
6. Don't-Care Conditions ($X$ or $d$): Optional states (such as invalid BCD digits $1010-1111$). Include $X$s in groups only when they enlarge a group of $1$s; otherwise, leave them unselected.

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4. Ladder Logic Architecture & PLC Programming (IEC 61131-3)

Ladder logic translates electrical relay ladder diagrams into programmable software rungs evaluated sequentially by a PLC processor.

PLC Cyclic Scan Execution

1. Input Scan: The PLC reads all physical digital and analog inputs and copies their states to the Input Image Table memory.
2. Program Logic Execution: The PLC evaluates ladder rungs sequentially from top-to-bottom and left-to-right.
3. Output Scan: The PLC writes updated output states from memory to the physical output terminals.
4. Housekeeping & Diagnostics: Communication processing and internal watchdog timer resets.

Core Ladder Logic Instructions

+-----------------------------------------------------------------------------------------+
|                            PLC LADDER INSTRUCTION REFERENCE                             |
+---------------------+-------------------+-----------------------------------------------+
| Instruction Name    | Ladder Symbol     | Logic Function & Bit Evaluation               |
+---------------------+-------------------+-----------------------------------------------+
| **Examine If Closed**| `----[  ]----`    | True (passes virtual power) if bit = 1 (High) |
| **(XIC / NO contact)**                   | False (blocks power) if bit = 0 (Low)         |
+---------------------+-------------------+-----------------------------------------------+
| **Examine If Open**  | `----[/]----`     | True (passes virtual power) if bit = 0 (Low)  |
| **(XIO / NC contact)**                   | False (blocks power) if bit = 1 (High)        |
+---------------------+-------------------+-----------------------------------------------+
| **Output Energize** | `----(  )----`    | Writes 1 to bit if rung is True;              |
| **(OTE / Coil)**                        | Writes 0 to bit if rung is False              |
+---------------------+-------------------+-----------------------------------------------+
| **Output Latch**    | `----( L )----`   | Sets bit to 1 when rung is True; stays 1      |
| **(OTL / Set)**                         | even if rung goes False (retentive)           |
+---------------------+-------------------+-----------------------------------------------+
| **Output Unlatch**  | `----( U )----`   | Resets latched bit to 0 when rung is True     |
| **(OTU / Reset)**                       |                                               |
+---------------------+-------------------+-----------------------------------------------+

PLC Timers (IEC 61131-3)

• On-Delay Timer (TON): When the rung transitions from False to True, the timer begins accumulating time (ACC). When ACC reaches the preset time (PRE), the Done bit (DN) turns ON ($1$). If the rung goes False before timing completes, ACC instantly resets to $0$.
• Off-Delay Timer (TOF): When the rung transitions from True to False, the output DN remains ON ($1$) and the timer accumulates time until ACC = PRE, at which point DN turns OFF ($0$).

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5. Industrial Control & Interlocking Circuits

3-Wire Start/Stop Motor Control with Seal-In Circuit

The standard 3-wire motor starter circuit provides low-voltage protection (LVP): if utility power fails, the holding circuit drops out and the motor will not automatically restart when power returns, preventing personnel injury.

 L1 (120 VAC / 24 VDC)                                                     L2 (Neutral / Com)
  +-------[ Stop PB ]-------+-------[ Start PB ]-------+-------[ Motor OL ]-------( Motor_M )---+
  |        (NC Field)       |        (NO Field)        |        (NC Contact)       Coil      |
  |                         |                          |                                         |
  |                         +-------[ M_Aux_NO ]-------+                                         |
  |                                  (Seal-In)                                                   |
  +----------------------------------------------------------------------------------------------+

Fail-Safe Field Wiring Rule for Stop Buttons

• Physical Field Wiring: Emergency stop and stop pushbuttons are physically wired using Normally Closed (NC) mechanical contacts in the field. If a control wire breaks or becomes disconnected, the circuit opens, creating a fail-safe shutdown.
• PLC Logic Programming: Because the physical Stop button is Normally Closed, it continuously delivers a $1$ ($24\text{ VDC}$) to the PLC input terminal in its normal unpressed state. Therefore, in the PLC ladder program, the Stop instruction must be programmed as an Examine If Closed (-[ ]- XIC) contact! When pressed, the input drops to $0$, the XIC instruction evaluates False, and the motor de-energizes.

Forward / Reverse Motor Starter Dual Interlocking

Reversing a 3-phase induction motor requires swapping two of the three incoming supply phases (e.g., L1 and L2). If both Forward and Reverse contactors pull in simultaneously, a direct phase-to-phase dead short occurs across the bus.

Rung 1: Forward Motor Starter
 |---[ Stop ]---+---[ Fwd_Start ]---+---[/_Rev_Aux_]----[ OL ]---( Fwd_Coil )---|
 |   (XIC)      |     (XIC)         |   (NC Aux Interlock)             (OTE)    |
 |              +---[ Fwd_Aux ]-----+                                           |

Rung 2: Reverse Motor Starter
 |---[ Stop ]---+---[ Rev_Start ]---+---[/_Fwd_Aux_]----[ OL ]---( Rev_Coil )---|
 |   (XIC)      |     (XIC)         |   (NC Aux Interlock)             (OTE)    |
 |              +---[ Rev_Aux ]-----+                                           |

• Electrical Interlocking: An auxiliary Normally Closed contact from the Reverse contactor (-[/]- Rev_Aux) is placed in series with the Forward coil, and an auxiliary NC contact from the Forward contactor (-[/]- Fwd_Aux) is placed in series with the Reverse coil.
• Mechanical Interlocking: A physical mechanical rocker bar physically prevents both contactor armatures from closing at the same time.

Automatic Transfer Switch (ATS) Emergency Logic

An Automatic Transfer Switch coordinates emergency backup generator power:

1. Utility Voltage Sensor (Device 27): Monitors normal utility voltage. If voltage drops below $80%$ for $> 1.0\text{ s}$, an engine start contact closes.
2. Generator Start & Warmup Timer (TON): Initiates generator cranking. Once generator reaches rated voltage and frequency (Device 84/59/81), a 3-5 second stabilization timer runs.
3. Transfer to Emergency: The ATS mechanism trips the Utility breaker and closes the Generator breaker (break-before-make transition).
4. Re-transfer to Utility Delay (TON): Upon utility restoration, a 15-30 minute timer ensures utility grid stability before re-transferring load.
5. Engine Cool-Down Timer (TOF): Generator runs unloaded for 5-10 minutes before shutdown.

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6. Comprehensive Worked Boolean Reduction & Ladder Logic Problem

Problem: Safety Interlock Boolean Minimization & Ladder Implementation

Scenario: An automated industrial conveyor system has four binary inputs:

• $A = \text{Safety Gate Closed}$ ($1 = \text{Closed/Safe}$)
• $B = \text{Emergency Stop OK}$ ($1 = \text{Healthy, Not Pressed}$)
• $C = \text{Conveyor Run Request}$ ($1 = \text{Run Requested}$)
• $D = \text{Motor Thermal Overload}$ ($1 = \text{Overload Tripped / Fault}$)

The conveyor motor output coil ($Y$) must energize when Safety Gate is Closed ($A=1$), Emergency Stop is OK ($B=1$), Run is Requested ($C=1$), and Overload is NOT Tripped ($D=0$). In addition, an authorized maintenance bypass mode energizes the motor if Maintenance Key ($M=1$) is active, Emergency Stop is OK ($B=1$), and Overload is NOT Tripped ($D=0$), regardless of Gate $A$ or Request $C$.

Derive:

1. The initial unsimplified Boolean expression for motor coil $Y$.
2. The minimized Boolean expression using algebraic axioms.
3. The resulting PLC ladder logic rung.

Execution Steps:
Step 1: Formulate Initial Boolean Equation
  Normal Path:   P1 = A * B * C * D'
  Bypass Path:   P2 = M * B * D'
  Total Logic:   Y = (A * B * C * D') + (M * B * D')

Step 2: Algebraic Simplification using Distributive Law
  Factor out common product term (B * D'):
  Y = (B * D') * (A * C + M)
  
  Expanded Minimal SOP Form:
  Y = A * B * C * D' + M * B * D'
  
  Factored Minimal Form:
  Y = B * D' * (A * C + M)

Step 3: Construct PLC Ladder Logic Rung
  Inputs in series represent AND operations; parallel branches represent OR operations.
  - B (E-Stop OK) is XIC contact: ----[ B ]----
  - D (Overload Tripped) is XIO contact: ----[/ D ]----
  - Parallel branch containing (A in series with C) OR (M):

  |----[ B ]----[/ D ]----+----[ A ]----[ C ]----+----( Y )----|
  |                       |                      |             |
  |                       +-------[ M ]----------+             |

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7. Common Exam Traps & Strategic Pitfalls

• Misinterpreting XIO with NC Pushbuttons: If a physical field pushbutton is Normally Closed (supplying a continuous $1$), an Examine If Closed (-[ ]- XIC) contact must be used in the PLC program to pass power when the button is unpressed. Using an XIO (-[/]-) contact on a physically NC button will cause the rung to be False during normal operation!
• Forgetting Dual-Interlocking in Motor Reversing: A motor reversing circuit must have both electrical auxiliary contact interlocks and mechanical interlocks. A question asking for complete protection requires cross-wiring NC auxiliary contacts in series with opposing coils.
• K-Map Wraparound Grouping Errors: The four corners of a 4-variable K-map (cells $m_0, m_2, m_8, m_{10}$) form a valid single group of 4 minterms, reducing to $\overline{B},\overline{D}$. Candidates frequently miss this grouping and write redundant 2-variable terms.
• De Morgan Inversion Errors: When simplifying $\overline{A + B \cdot C}$, students often write $\overline{A} \cdot \overline{B} + \overline{C}$ instead of the correct form $\overline{A} \cdot \overline{BC} = \overline{A} \cdot (\overline{B} + \overline{C}) = \overline{A},\overline{B} + \overline{A},\overline{C}$.