6.1 PCB Design, Layered Construction & Manufacturing

6.1 PCB Design, Layered Construction & Manufacturing

Modern aircraft avionics systems—including Full Authority Digital Engine Controls (FADEC), Flight Management Computers (FMC), Electronic Flight Instrument Systems (EFIS), and Air Data Inertial Reference Units (ADIRU)—rely on Printed Circuit Boards (PCBs) as the physical and electrical backbone of their Line Replaceable Units (LRUs). Under European Aviation Safety Agency (EASA) Part-66 Module 04, certifying aircraft maintenance engineers must understand the materials, manufacturing processes, layered stackups, and component mounting technologies that ensure circuit card assemblies survive severe aerospace environmental stresses, including rapid thermal cycling ($-55^\circ\text{C}$ to $+85^\circ\text{C}$ or higher), engine vibration, altitude decompression, and chemical exposure.

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Substrate Materials in Aviation Electronics

The PCB substrate provides mechanical support for components, structural rigidity under high-G maneuvers and acoustic vibration, and electrical insulation between conductive conductors. The dielectric properties, thermal endurance, and moisture resistance of the substrate dictate its operational boundary within the airframe:

1. FR-4 (Flame-Retardant Woven Fiberglass / Epoxy)

• Composition: Woven fiberglass cloth impregnated with a flame-retardant epoxy resin binder.
• Dielectric Properties: Relative dielectric constant $\epsilon_r \approx 4.3\text{ to } 4.7$ (nominal $\approx 4.5$ at $1\text{ MHz}$); dielectric loss tangent $\tan\delta \approx 0.015\text{ to } 0.020$.
• Thermal Performance: Standard FR-4 exhibits a glass transition temperature ($T_g$) of approximately $130^\circ\text{C}\text{ to } 140^\circ\text{C}$ (high-$T_g$ variants reach $170^\circ\text{C}\text{ to } 180^\circ\text{C}$). The continuous maximum operating temperature is typically rated at $130^\circ\text{C}$. Above $T_g$, the polymer matrix transitions from a rigid, glassy state to a flexible, rubbery state, precipitating a steep increase in the coefficient of thermal expansion (CTE), especially along the vertical Z-axis.
• Moisture Absorption: Exceptionally low, strictly specified at $< 0.15%$ by weight per IPC-4101. Excess moisture absorption alters the dielectric constant and risks internal steam delamination during soldering or high-altitude depressurization.
• Avionics Application: The standard baseline substrate for pressurized cockpit, cabin, and avionic equipment bay LRUs (e.g., VHF transceivers, audio control panels, passenger entertainment modules).

2. Polyimide (High-Temperature & Flex Substrates)

• Composition: Thermoset polyimide resin reinforced with woven glass or manufactured as unreinforced thin films (e.g., Kapton).
• Thermal Endurance: Exceptional thermal stability with $T_g > 250^\circ\text{C}$ to $260^\circ\text{C}$ and continuous service temperatures exceeding $200^\circ\text{C}$. Polyimide withstands soldering temperatures without softening or blistering.
• Mechanical Flexibility: In thin film formats ($25\text{ to } 125\ \mu\text{m}$), polyimide provides superior tensile strength, ductility, and fatigue resistance under cyclic bending. This enables the fabrication of flexible printed circuits (flex-PCBs) and hybrid rigid-flex assemblies.
• Avionics Application: Critical for interconnecting sensors and actuators routed through cramped, moving, or unpressurized airframe structures—such as wing leading-edge slats, folding wing mechanisms, landing gear wheel wells, and engine nacelle sensor interfaces where rigid wiring harnesses would be too bulky, heavy, or prone to fatigue failure.

3. Ceramic / Alumina ($Al_2O_3$) & Aluminum Nitride ($AlN$)

• Composition: Sintered inorganic crystalline matrices of aluminum oxide ($96%\text{ to } 99.6%\ Al_2O_3$) or aluminum nitride ($AlN$).
• Thermal & Dielectric Advantages: Unmatched thermal conductivity ($20\text{ to } 30\text{ W/(m}\cdot\text{K)}$ for alumina and up to $180\text{ W/(m}\cdot\text{K)}$ for $AlN$, compared to a dismal $0.25\text{ W/(m}\cdot\text{K)}$ for FR-4). They feature a low dielectric loss tangent ($\tan\delta < 0.001$), stable dielectric constant ($\epsilon_r \approx 9.0\text{ to } 10.0$), and a low coefficient of thermal expansion ($CTE \approx 6\text{ to } 7\text{ ppm/}^\circ\text{C}$) that closely matches bare silicon and gallium arsenide (GaAs) semiconductor dies.
• Avionics Application: S-band, X-band, and Ka-band weather radar transceivers, radar altimeter RF front-ends, active electronically scanned array (AESA) transmit/receive (T/R) modules, and high-power FADEC engine actuator switching bridges where heavy heat dissipation and ultra-low microwave dielectric attenuation are mandatory.

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Manufacturing & Subtractive Chemical Etching

The fabrication of aviation circuit boards is predominantly a subtractive photolithographic process, wherein unwanted copper is chemically dissolved from a copper-clad laminate base:

1. Base Copper-Clad Laminate (CCL): Fabrication begins with a core dielectric sheet clad on one or both sides with high-purity electrodeposited copper foil. Copper thickness is commercially specified in ounces of copper per square foot: standard $1\text{ oz/ft}^2$ corresponds to a nominal foil thickness of $35\ \mu\text{m}$ ($1.4\text{ mils}$), while $2\text{ oz/ft}^2$ corresponds to $70\ \mu\text{m}$ ($2.8\text{ mils}$) for high-current power distribution traces.
2. Photoresist Application: The copper surface is chemically cleaned and laminated with a uniform, light-sensitive polymeric film called photoresist (commonly a dry film photoresist applied under heated pressure rollers).
3. UV Photolithographic Exposure: A precision photographic film tool or direct-imaging laser (LDI) exposes the board to intense ultraviolet (UV) radiation through a photomask. In a negative-acting photoresist, UV photons induce cross-linking polymerization in the exposed areas (the desired circuit tracks), rendering them insoluble in developing chemistry. The unexposed areas remain monomeric and soluble.
4. Chemical Development: The board passes through a developing chamber sprayed with a mild alkaline solution (such as $1%$ sodium carbonate, $Na_2CO_3$). The unexposed, unpolymerized photoresist dissolves and washes away, leaving the bare unwanted copper exposed while the polymerized resist protects the intended circuit tracks.
5. Subtractive Chemical Etching: The panel enters an acid or alkaline chemical etching conveyor. The exposed, unprotected copper is dissolved away via chemical oxidation. Two primary industrial etchants are employed:
   • Ferric Chloride ($FeCl_3$): An acidic etchant widely used for high-precision etching: $Cu + 2FeCl_3 \longrightarrow CuCl_2 + 2FeCl_2$ Solid metallic copper reduces ferric ions ($Fe^{3+}$) to ferrous ions ($Fe^{2+}$), dissolving copper into cupric chloride ($CuCl_2$).
   • Ammonium Persulfate ($(NH_4)_2S_2O_8$): An alternative acidic oxidizer: $Cu + (NH_4)_2S_2O_8 \longrightarrow CuSO_4 + (NH_4)_2SO_4$
6. Photoresist Stripping: Once etching is complete, the protective polymerized resist is stripped using a stronger alkaline solution (e.g., $3%\text{ to } 5%$ sodium hydroxide, $NaOH$, or potassium hydroxide, $KOH$), revealing the pristine, isolated conductive copper traces.

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Surface Finishes, Legends & Conformal Coating

Bare copper rapidly oxidizes in ambient air, forming non-conductive copper oxides ($CuO$, $Cu_2O$) that prevent reliable solder wetting. Furthermore, bare boards must be protected against operating environments:

Solder Mask (Solder Resist)

A durable, liquid photoimageable (LPI) epoxy resin layer is coated onto the outer board surfaces, exposed via photolithography, and thermally cured. Solder mask (typically green, blue, or amber in aerospace) covers the entire PCB except for the component soldering lands and test points. Its primary functions are:

• Preventing unintended solder bridging (electrical short circuits) between closely spaced conductor pins during automated wave or reflow soldering.
• Protecting the underlying thin copper tracks from atmospheric oxidation and minor physical scratching during maintenance handling.

Silkscreen Legend (Component Identification)

A permanent epoxy marking ink is screen-printed or inkjet-printed onto the cured solder mask. The silkscreen provides essential technical references for avionics technicians:

• Reference Designators: Alphanumeric symbols identifying discrete components per IEEE/ANSI standards (e.g., $R_1, R_2$ for resistors; $C_{12}$ for capacitors; $L_3$ for inductors; $D_4$ for diodes; $Q_1$ for transistors; $U_2$ or $IC_3$ for integrated circuits).
• Polarity & Orientation Marks: Cathode bands for diodes, positive ($+$) symbols for polarized electrolytic and tantalum capacitors, and notch/dot indicators marking Pin 1 on dual in-line (DIP) and quad flat-pack (QFP) ICs.

Conformal Coating (MIL-I-46058C / IPC-CC-830)

Avionics circuit cards are subjected to altitude chamber pressure differentials, rapid climb/descent temperature swings causing internal atmospheric condensation, salt-laden marine air, turbine exhaust gases, and aggressive hydraulic fluids (such as phosphate-ester Skydrol). To ensure survival, assembled boards receive a conformal coating—a thin polymeric dielectric layer ($25\text{ to } 75\ \mu\text{m}$ thick) conforming perfectly to board contours:

1. Acrylic (AR): Easy to apply and rework; soluble in organic solvents (e.g., chlorinated solvents or methyl ethyl ketone). Moderate moisture resistance; poor chemical/solvent resistance.
2. Polyurethane (UR): Outstanding moisture, chemical, and fuel resistance; excellent dielectric isolation. Rework is challenging, requiring thermal decomposition with a specialized stripping iron or mechanical abrading.
3. Silicone (SR): Superior thermal endurance ($-65^\circ\text{C}$ to $+200^\circ\text{C}$); high flexibility and vibration damping; thickest coating ($50\text{ to } 200\ \mu\text{m}$). Widely used in engine nacelles and high-vibration avionics.
4. Parylene (XY): Vacuum-deposited vapor-phase poly-para-xylylene. Forms a pinhole-free, ultra-thin ($12\text{ to } 50\ \mu\text{m}$), uniform coating penetrating underneath dense SMT components with zero meniscus pull. Applied in mission-critical space and flight-control computers.

[!WARNING] Conformal Coating Stripping Hazard: When desoldering components during LRU depot-level repair, technicians must strictly remove the conformal coating around the joint using approved chemical strippers or thermal de-coaters before applying soldering irons. Vaporizing polyurethane or silicone with a soldering iron generates toxic fumes (including isocyanates) and carbonizes the coating residue into the joint, causing solder contamination and high-resistance open circuits.

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Multilayer Stackups, Power Planes & Controlled Impedance

While legacy general-aviation systems utilized single-sided or double-sided PCBs, modern digital avionics computers universally employ multilayer PCBs containing 4, 6, 8, 12, or up to 24 conductive layers laminated under intense heat and pressure with intermediate fiberglass-epoxy bonding sheets called prepreg (pre-impregnated B-stage resin).

graph TD
    subgraph Stackup["Multilayer Avionics Stackup (4-Layer Example)"]
        L1["Layer 1 (Top Signal): SMT Pads, Microstrip High-Speed Tracks"] 
        D1["Dielectric Core Substrate (FR-4 / Polyimide)"]
        L2["Layer 2 (Internal GND Plane): Solid Copper 0V Reference & Shield"]
        D2["Prepreg Bonding Sheet (Epoxy Resin Glass Cloth)"]
        L3["Layer 3 (Internal Power Plane): Split V_CC Rails (+28V, +5V, +3.3V)"]
        D3["Dielectric Core Substrate (FR-4 / Polyimide)"]
        L4["Layer 4 (Bottom Signal): Secondary Routing & THT Solder Lands"]
    end
    L1 --- D1 --- L2 --- D2 --- L3 --- D3 --- L4

Dedicated Internal Ground and Power Planes

In a professional avionics stackup, inner layers are reserved as continuous solid sheets of copper dedicated to Ground ($GND$) and DC Power ($V_{CC}$):

1. Low-Impedance Power Distribution: Solid planes present virtually zero DC resistance and minimal parasitic loop inductance, preventing high-frequency voltage spikes and ground bounce caused by simultaneous digital IC output switching.
2. Distributed Plane Capacitance: The microscopic dielectric spacing between closely spaced power and ground planes forms an intrinsic parallel-plate capacitor ($C = \epsilon_0 \epsilon_r A / d$) that shunts ultra-high-frequency supply noise directly to ground, acting as a built-in, distributed bypass capacitor across the entire board.
3. Electromagnetic Shielding (EMI/EMC): Continuous copper planes act as electrostatic Faraday shields, containing radiated RF fields generated by internal processor clocks and preventing external airborne radar/radio transmissions from coupling into high-impedance analog lines.
4. Controlled Transmission Line Impedance ($Z_0$): High-speed digital avionics data buses—including ARINC 429 ($75\text{ to } 78\ \Omega$), AFDX/Ethernet ($100\ \Omega$ differential), and MIL-STD-1553 ($77\ \Omega$)—cannot be treated as simple lumped connections. They behave as distributed transmission lines. By routing signal traces over an unbroken reference ground plane with precise trace width ($w$) and dielectric height ($h$), the line's characteristic impedance ($Z_0$) is strictly matched to prevent signal reflections, ringing, and data frame corruption.

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Plated Through-Holes (PTH) & Via Architectures

To route electrical signals and power across different layers in a multilayer stackup, holes are drilled through the board and metallized. Fabricating a Plated Through-Hole (PTH) involves a multi-stage chemical process:

1. Precision CNC Drilling: High-speed mechanical spindles (up to $250,000\text{ RPM}$) or UV/CO$_2$ lasers drill holes through the laminated stack.
2. Chemical Desmearing: Friction during mechanical drilling melts epoxy resin, smearing it across the exposed internal copper plane edges inside the hole. The panel is processed through an alkaline permanganate or plasma chamber to dissolve and etch away this resin smear, exposing bare copper ring contacts.
3. Electroless Copper Deposition: Because the drilled fiberglass barrel wall is an electrical insulator, the board is immersed in a catalyst bath of colloidal palladium-tin, followed by an electroless copper bath (an autocatalytic chemical reduction of cupric ions using formaldehyde in alkaline solution). This deposits an ultra-thin ($0.5\text{ to } 1.0\ \mu\text{m}$), continuous conductive copper seed layer over the entire hole barrel wall.
4. Electrolytic Copper Plating: The panel is placed in an electroplating acid copper sulfate tank. Direct electrical current plates ductile copper onto the seeded barrel walls until a robust, continuous metallization barrel thickness of at least $25\ \mu\text{m}$ ($1.0\text{ mil}$) is built up per military and IPC Class 3 standards.

Via Classifications

• Through-Hole Via: Drilled through the entire board stackup from the top surface to the bottom surface. Simple and inexpensive to manufacture, but consumes routing real estate on every single layer it traverses.
• Blind Via: Originates on an external surface layer (top or bottom) and terminates on an internal layer without penetrating the opposite side. Drilled either mechanically before lamination or via laser ablation.
• Buried Via: Connects two or more internal layers entirely within the core of the PCB, completely encapsulated within the stackup and invisible from either external surface.
• Microvia: Laser-drilled small-diameter vias (typically $\le 150\ \mu\text{m}$) spanning a single dielectric layer in High-Density Interconnect (HDI) boards, essential for escaping fine-pitch Ball Grid Array (BGA) flight processors.

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Component Mounting: THT versus SMT

Avionics circuit cards incorporate two distinct component assembly technologies, each possessing distinct structural, electrical, and thermal characteristics:

graph LR
    subgraph THT_Tech["Through-Hole Technology (THT)"]
        T1["Component Lead"] --> T2["Inserted Through Drilled PTH Barrel"]
        T2 --> T3["360-degree Solder Barrel Fill"]
        T3 --> T4["High Mechanical Shear/Pull Anchorage"]
    end
    subgraph SMT_Tech["Surface Mount Technology (SMT)"]
        S1["Lead / Solder Ball"] --> S2["Placed Directly onto Surface Copper Pad"]
        S2 --> S3["Reflow Solder Joint"]
        S3 --> S4["High Density, Low Parasitic Inductance"]
    end

1. Through-Hole Technology (THT)

• Mechanism: Component wire leads or terminal pins are inserted through drilled, plated through-holes (PTH) in the PCB and soldered from the opposite side, typically via an automated wave soldering machine or manual aerospace hand soldering.
• Mechanical Strength: Unrivaled mechanical anchorage. The solder completely fills the vertical copper barrel, encasing the lead in a $360^\circ$ metallurgical bond that distributes mechanical stress throughout the entire thickness of the board substrate.
• Avionics Application: Indispensable for heavy, high-mass, or high-stress components subject to severe airframe acoustic vibration and high-G maneuvers—such as primary power supply transformers, heavy filter chokes, power relays, chassis-grounded power transistors on heat sinks, and rugged multi-pin MIL-DTL-38999 circular external interface connectors subjected to repeated cable harness mating forces.

2. Surface Mount Technology (SMT / SMD)

• Mechanism: Surface Mount Devices (SMDs) feature flat metallized end-caps, gull-wing leads, J-leads, or bottom-side solder ball arrays (Ball Grid Arrays - BGAs). Components are placed directly onto solder-paste-stenciled surface copper lands/pads using high-speed automated pick-and-place robots, followed by heating in a multi-zone convection reflow soldering oven.
• Component Density: Eliminates the need for drilled through-holes for every lead. Components can be populated on both the top and bottom surfaces of the board, reducing total LRU volume and weight by up to $60%\text{ to } 80%$.
• Electrical Performance at High Frequencies: Eliminating long component wire leads dramatically reduces parasitic lead inductance ($L_{lead} < 1\text{ nH}$ for SMT vs $5\text{ to } 10\text{ nH}$ for THT) and stray capacitance. This reduction in parasitics is mandatory for multi-megahertz and gigahertz clock processors, ARINC 664 (AFDX) transceivers, and radar digital signal processors where lead inductance would distort pulse rise times and cause severe ringing.

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Worked Engineering Calculations

Calculation 1: Characteristic Impedance ($Z_0$) of an Avionics Microstrip Trace

An avionics design engineer is routing an ARINC 429 digital data bus track on the top layer of an LRU flight computer board. The layer stackup uses an FR-4 dielectric substrate (dielectric constant $\epsilon_r = 4.5$) situated directly over an unbroken internal ground plane (Layer 2).

• Dielectric substrate thickness between Layer 1 and Layer 2: $h = 0.80\text{ mm}$
• Copper trace thickness ($1\text{ oz}$ copper): $t = 35\ \mu\text{m} = 0.035\text{ mm}$
• Copper trace width: $w = 1.45\text{ mm}$

Using the standard IPC-2141 microstrip characteristic impedance formula for a surface conductor over a ground plane: $Z_0 = \frac{87}{\sqrt{\epsilon_r + 1.41}} \ln\left( \frac{5.98 h}{0.8 w + t} \right)$

Step 1: Calculate the denominator of the logarithmic argument

$\text{Denominator} = 0.8 w + t = (0.8 \times 1.45\text{ mm}) + 0.035\text{ mm} = 1.160 + 0.035 = 1.195\text{ mm}$

Step 2: Calculate the numerator of the logarithmic argument

$\text{Numerator} = 5.98 h = 5.98 \times 0.80\text{ mm} = 4.784\text{ mm}$

Step 3: Compute the ratio and natural logarithm

$\text{Ratio} = \frac{4.784}{1.195} \approx 4.0033$ $\ln(4.0033) \approx 1.3871$

Step 4: Calculate the pre-factor and final characteristic impedance

$\sqrt{\epsilon_r + 1.41} = \sqrt{4.5 + 1.41} = \sqrt{5.91} \approx 2.4310$ $Z_0 = \frac{87}{2.4310} \times 1.3871 = 35.787 \times 1.3871 \approx 49.64\ \Omega \approx 50\ \Omega$

Engineering Conclusion: The calculated characteristic impedance is nominally $50\ \Omega$, precisely matching the transmission line specification required for high-speed single-ended digital avionics lines.

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Calculation 2: DC Power Track Resistance & Voltage Drop

An internal $+28\text{ V DC}$ power bus track on an aircraft circuit card delivers continuous power to an actuator driver module:

• Copper foil specification: $2\text{ oz/ft}^2$ (thickness $t = 70\ \mu\text{m} = 7.0 \times 10^{-5}\text{ m}$)
• Trace width: $w = 2.50\text{ mm} = 2.50 \times 10^{-3}\text{ m}$
• Trace length: $L = 250\text{ mm} = 0.250\text{ m}$
• Resistivity of copper at operating temperature ($+60^\circ\text{C}$): $\rho_{Cu} = 1.95 \times 10^{-8}\ \Omega\cdot\text{m}$
• Continuous DC current load: $I = 4.00\text{ A}$

Step 1: Calculate the cross-sectional area ($A$) of the copper track

$A = w \times t = (2.50 \times 10^{-3}\text{ m}) \times (7.0 \times 10^{-5}\text{ m}) = 1.75 \times 10^{-7}\text{ m}^2$

Step 2: Compute DC trace resistance ($R_{trace}$)

$R_{trace} = \rho \frac{L}{A} = (1.95 \times 10^{-8}\ \Omega\cdot\text{m}) \times \frac{0.250\text{ m}}{1.75 \times 10^{-7}\text{ m}^2} = \frac{4.875 \times 10^{-9}}{1.75 \times 10^{-7}} = 0.02786\ \Omega = 27.86\text{ m}\Omega$

Step 3: Determine the DC voltage drop ($\Delta V$) along the trace

$\Delta V = I \times R_{trace} = 4.00\text{ A} \times 0.02786\ \Omega = 0.1114\text{ V} = 111.4\text{ mV}$

Step 4: Calculate electrical power dissipated as heat in the trace ($P_{diss}$)

$P_{diss} = I^2 \times R_{trace} = (4.00\text{ A})^2 \times 0.02786\ \Omega = 16 \times 0.02786 = 0.4458\text{ W} = 445.8\text{ mW}$

Avionics Maintenance Significance: The track drops only $111.4\text{ mV}$ from the nominal $28\text{ V}$ bus (a minor $0.4%$ drop, well within the allowable $2%$ line regulation allowance), but dissipates nearly $0.45\text{ W}$ along its $25\text{ cm}$ length, highlighting why thermal plane conduction and adequate track width per IPC-2152 are critical to prevent localized PCB hot spots.