5.3 Active Wave-Shaping, Comparators & Digital Logic Basics

5.3 Active Wave-Shaping, Comparators & Digital Logic Basics

While linear operational amplifier circuits employ negative feedback to scale and mix analog signals, modern flight management systems, air data computers, and engine control units also require non-linear decision-making, dynamic waveform generation, and digital processing. Non-linear op-amp configurations exploit open-loop saturation or positive feedback to compare signal thresholds, while dynamic reactive feedback circuits perform mathematical integration and differentiation. Furthermore, analog sensors ultimately interface with digital flight computers via discrete logic gates and bistable storage elements. Under EASA Part-66 Module 04, aircraft maintenance engineers must understand the operation, transfer characteristics, and maintenance safeguards for comparators, Schmitt triggers, active wave-shapers, and digital logic families.

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Voltage Comparators & The Schmitt Trigger

The Open-Loop Voltage Comparator

A voltage comparator is designed to determine which of two input voltages is greater. Unlike linear amplifiers, a comparator operates in an open-loop configuration with no feedback:

graph LR
    subgraph OpenLoopComparator["Voltage Comparator Operation"]
        VP["Non-Inverting Input (V+)"] --> COMP["Op-Amp Comparator<br/>No Feedback (Open-Loop)"]
        VM["Inverting Input (V- / V_ref)"] --> COMP
        COMP --> OUT["Output Voltage (V_out)<br/>Saturates at +V_sat or -V_sat"]
    end

Because open-loop gain is enormous ($A_{OL} \ge 10^5$), even a microvolt difference between inputs forces the output stage into full saturation:

• If $V^+ > V^-$, then $V_{out} = +V_{sat} \approx +V_{CC} - 1.5\text{ V}$ (Logic High / Alarm Trip)
• If $V^+ < V^-$, then $V_{out} = -V_{sat} \approx -V_{EE} + 1.5\text{ V}$ (Logic Low / Normal)

In a zero-crossing detector, the inverting terminal is grounded ($V_{ref} = 0\text{ V}$), producing an output that transitions whenever the input signal passes through zero. In level detectors, a fixed reference voltage ($V_{ref}$) is established on one terminal via a Zener diode or precision voltage divider. For instance, in an aircraft cabin altitude warning circuit, a barometric pressure sensor voltage is compared to a reference corresponding to $10,000\text{ ft}$; if cabin pressure drops below the threshold, the comparator output snaps to $+V_{sat}$, illuminating the cockpit master warning and deploying passenger oxygen masks.

The Noise Problem & The Schmitt Trigger Solution

When a slowly changing analog sensor signal contains electrical noise (such as induced $400\text{ Hz}$ AC hum or electromagnetic interference from fuel pumps), the signal crosses the reference threshold multiple times during its transition. In an open-loop comparator, this causes the output to toggle violently between positive and negative saturation—a failure mode known as output chatter or contact bounce, which can burn out downstream indicator relays.

To eradicate chatter, the Schmitt trigger incorporates positive feedback by routing a portion of the output voltage back to the non-inverting ($+$) input terminal via a voltage divider ($R_1$ and $R_f$):

                          +------------[ Rf ]------------+
                          |                              |
                          |    |\                        |
                          +----| +\                      |
                          |    |   \                     |
                         [R1]  |    >--------------------+----o V_out
                          |    |   / 
                         GND   | -/  
                               |/    
                               |
  V_in o-----------------------+

Positive feedback creates two distinct switching thresholds, establishing a hysteresis band ($V_H$):

1. Upper Trip Point ($V_{UTP}$): When the output is initially at $+V_{sat}$: $V_{UTP} = +V_{sat} \left( \frac{R_1}{R_1 + R_f} \right)$
2. Lower Trip Point ($V_{LTP}$): When the output is at $-V_{sat}$: $V_{LTP} = -V_{sat} \left( \frac{R_1}{R_1 + R_f} \right)$
3. Hysteresis Voltage ($V_H$): $V_H = V_{UTP} - V_{LTP}$

As the input voltage rises, the output will not switch from $+V_{sat}$ to $-V_{sat}$ until $V_{in}$ exceeds $V_{UTP}$. Once switched, any noise on the input cannot switch the output back unless the signal drops completely below the lower threshold $V_{LTP}$. As long as peak-to-peak noise amplitude is less than $V_H$, false triggering is eliminated.

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Active Op-Amp Wave-Shaping Circuits

The Active Integrator

An active op-amp integrator performs mathematical time-integration of the input voltage. It is constructed by placing a capacitor ($C$) in the negative feedback path and an input resistor ($R$) on the inverting terminal, with the non-inverting terminal grounded ($0\text{ V}$):

                               +------------[ C ]------------+
                               |                             |
                               |    |\                       |
  V_in o----[ R ]--------------+----| -\                     |
                                    |   \                    |
                               0V --| +  >-------------------+----o V_out
                                    |   / 
                                    |/    

1. By virtual ground, $V^- = 0\text{ V}$. Current entering the summing junction is: $I_{in}(t) = \frac{V_{in}(t) - 0}{R} = \frac{V_{in}(t)}{R}$
2. The current charging the feedback capacitor is governed by the capacitor $I$-$V$ relation: $I_C(t) = C \frac{d(0 - V_{out})}{dt} = -C \frac{dV_{out}(t)}{dt}$
3. Since $I_{in} = I_C$ (op-amp input current is zero): $\frac{V_{in}(t)}{R} = -C \frac{dV_{out}(t)}{dt} \implies \frac{dV_{out}(t)}{dt} = -\frac{V_{in}(t)}{RC}$
4. Integrating both sides with respect to time from $0$ to $t$: $V_{out}(t) = -\frac{1}{RC} \int_0^t V_{in}(t)\,dt + V_{out}(0)$

Wave-Shaping Dynamics & Applications:

• Constant DC Input: A constant positive DC input produces a downward-sloping linear voltage ramp; a negative DC input produces an upward-sloping linear ramp.
• Square Wave Input: Integrating a symmetrical square wave generates a linear triangular wave.
• Practical DC Stabilization: At $0\text{ Hz}$ (DC), capacitor reactance is infinite ($X_C \to \infty$), leaving the op-amp in an open-loop state where tiny input offset voltages quickly saturate the output. Practical aircraft integrators place a large shunt resistor ($R_f \approx 10R$) in parallel with $C$ to limit DC gain.
• Avionics Application: Autopilot pitch rate integration (integrating pitch angular rate $\dot{\theta}$ from a rate gyro to determine absolute aircraft pitch attitude $\theta$) and analog weather radar sweep generators.

The Active Differentiator

An active op-amp differentiator produces an output proportional to the rate of change of the input signal. The positions of the resistor and capacitor are reversed: capacitor $C$ is on the input, and resistor $R$ forms the feedback path:

                               +------------[ R ]------------+
                               |                             |
                               |    |\                       |
  V_in o----||-----------------+----| -\                     |
            C                       |   \                    |
                               0V --| +  >-------------------+----o V_out
                                    |   / 
                                    |/    

1. Input current through capacitor $C$ is: $I_{in}(t) = C \frac{dV_{in}(t)}{dt}$
2. Feedback current through resistor $R$ is: $I_f(t) = \frac{0 - V_{out}(t)}{R} = -\frac{V_{out}(t)}{R}$
3. Equating $I_{in} = I_f$: $C \frac{dV_{in}(t)}{dt} = -\frac{V_{out}(t)}{R} \implies V_{out}(t) = -RC \frac{dV_{in}(t)}{dt}$

Severe Maintenance & Design Limitation: Because differentiator gain increases linearly with frequency ($A_v(\omega) = \omega RC$), the circuit severely amplifies high-frequency noise. In aircraft installations, $400\text{ Hz}$ ripple or radio frequencies produce violent output spikes. Practical avionics differentiators must include a small series resistor ($R_s$) in front of $C$ and a small parallel capacitor ($C_f$) across $R$ to roll off high-frequency gain above a safe cutoff frequency.

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Digital Logic Fundamentals & Logic Families

Digital avionics systems—such as Full Authority Digital Engine Controls (FADEC), Air Data Computers (ADC), and Flight Management Systems (FMS)—process analog sensor inputs by converting them into binary information governed by two discrete electrical voltage states:

• Logic 1 (HIGH): True / Asserted state.
• Logic 0 (LOW): False / De-asserted state.

Comparison of Major IC Logic Families: TTL vs. CMOS

Aircraft electronics utilize two primary digital integrated circuit families:

[!WARNING] CMOS ESD Protocol in Aircraft Line Maintenance: CMOS integrated circuits feature gate oxide dielectric insulation layers less than $10\text{ nm}$ thick that suffer permanent dielectric puncture when exposed to static potentials as low as $50\text{ to }100\text{ V}$. Technicians must always utilize grounded conductive wrist straps, static-dissipative workbench mats, and transport avionics circuit boards in conductive metallized shielding bags.

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Basic & Universal Logic Gates

Digital decisions are executed by fundamental logic gates governed by Boolean algebra and De Morgan's theorems:

graph LR
    subgraph UniversalGates["De Morgan's Equivalence & Universality"]
        NAND1["NAND Gate: Y = (A · B)'"] --- EQ1["Equivalent to"] --- NOR_IN["Negative-OR: Y = A' + B'"]
        NOR1["NOR Gate: Y = (A + B)'"] --- EQ2["Equivalent to"] --- NAND_IN["Negative-AND: Y = A' · B'"]
    end

Universality of NAND and NOR Gates

NAND and NOR gates are designated universal logic gates because any Boolean function (AND, OR, NOT, XOR) can be constructed exclusively from NAND gates or exclusively from NOR gates, significantly reducing inventory requirements for aircraft line-replaceable unit (LRU) manufacturing.

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Bistable Storage Elements (Flip-Flops)

Combinational logic gates produce outputs based solely on current inputs. To store flight data, register system status, and sequence operations, digital systems require sequential logic circuits known as bistable multivibrators (flip-flops).

1. The Set-Reset (SR) Latch

The basic memory cell is formed by cross-coupling two NOR gates (active-high inputs) or two NAND gates (active-low inputs):

• $S=1, R=0$ (Set): Output $Q$ transitions to $1$, $\overline{Q}$ transitions to $0$.
• $S=0, R=1$ (Reset): Output $Q$ transitions to $0$, $\overline{Q}$ transitions to $1$.
• $S=0, R=0$ (Hold / Memory): Outputs maintain their prior state indefinitely.
• $S=1, R=1$ (Invalid / Forbidden): In a NOR latch, this forces both $Q$ and $\overline{Q}$ to $0$ simultaneously, violating their complementary definition. If inputs transition back to zero simultaneously, race conditions produce an unpredictable state.

2. The Clocked D-Type Flip-Flop

The D (Data) flip-flop resolves the invalid state of the SR latch. It samples the single $D$ input on the active transition (rising or falling edge) of a clock pulse ($CLK$):

$Q_{next} = D$

• Avionics Frequency Division: When the inverted output $\overline{Q}$ is tied directly back to the $D$ input, the flip-flop toggles its output state on every active clock edge. This divides the incoming clock frequency by precisely two ($f_{out} = f_{in} / 2$). Cascading multiple D flip-flops creates digital binary counter chains and clock prescalers used in flight computers.

3. The JK Flip-Flop

The JK flip-flop represents the most versatile bistable element, eliminating the undefined state of the SR latch:

• $J=0, K=0$: Memory / Hold ($Q_{next} = Q$).
• $J=0, K=1$: Reset ($Q_{next} = 0$).
• $J=1, K=0$: Set ($Q_{next} = 1$).
• $J=1, K=1$ (Toggle Mode): Output reverses its state on each clock pulse ($Q_{next} = \overline{Q}$).

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Worked Numerical Calculation: Active Integrator Ramp Output

An active integrator stage in an aircraft radar horizontal sweep generator utilizes an input resistor of $R = 250\text{ k}\Omega$ and a feedback capacitor of $C = 0.047\ \mu\text{F}$. An initial DC voltage of $-2.0\text{ V}$ is applied to the input for a duration of $\Delta t = 25\text{ ms}$. Assuming the initial capacitor voltage is $V_{out}(0) = 0\text{ V}$, calculate the slope of the voltage ramp and the final output voltage.

Step 1: Calculate the Circuit Time Constant ($\tau = RC$)

$\tau = R \cdot C = (250 \times 10^3\ \Omega) \times (0.047 \times 10^{-6}\text{ F}) = 0.01175\text{ s} = 11.75\text{ ms}$

Step 2: Determine the Rate of Change (Ramp Slope)

$\frac{dV_{out}}{dt} = -\frac{V_{in}}{RC} = -\frac{-2.0\text{ V}}{0.01175\text{ s}} = +170.21\text{ V/s} = +0.1702\text{ V/ms}$

Step 3: Compute Output Voltage After $25\text{ ms}$

$V_{out}(t) = -\frac{V_{in}}{RC} \cdot t + V_{out}(0)$ $V_{out}(25\text{ ms}) = (+170.21\text{ V/s}) \times (0.025\text{ s}) + 0\text{ V} = +4.255\text{ V} \approx +4.26\text{ V}$

Conclusion: The integrator generates a clean linear positive-going ramp climbing to $+4.26\text{ V}$ at $25\text{ ms}$, operating well clear of the $+13.5\text{ V}$ saturation limit.