4.3 Field Effect Transistors & Darlington Pairs

4.3 Field Effect Transistors & Darlington Pairs

While Bipolar Junction Transistors (BJTs) are current-controlled devices relying on both majority and minority charge carriers, Field Effect Transistors (FETs) operate on a fundamentally different semiconductor principle: unipolar conduction controlled by an electrostatic field.

In avionics systems, FETs offer critical advantages over BJTs, including ultra-high input impedance, near-zero DC gate drive current, low thermal noise figures, and superior thermal stability without thermal runaway. Alongside FETs, the composite bipolar Darlington pair provides extreme current amplification required to interface microelectronic flight computers with high-current electro-mechanical aircraft actuators.

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1. Unipolar vs. Bipolar Operation: Voltage vs. Current Control

Understanding the foundational distinction between BJTs and FETs is a primary EASA Part-66 Module 04 requirement:

• BJT (Bipolar): Conduction depends on two carrier types (electrons and holes). It is a current-controlled device where a small base current ($I_B$) controls a large collector current ($I_C = \beta I_B$). Its forward-biased base-emitter junction exhibits moderate input impedance ($1\text{ k}\Omega\text{ to }5\text{ k}\Omega$).
• FET (Unipolar): Current conduction is carried exclusively by one carrier type (majority electrons in an N-channel, or majority holes in a P-channel) traveling between Source ($S$) and Drain ($D$). Current flow is modulated by an electric field established by a voltage applied to the Gate ($G$) terminal. Because the gate draws virtually zero DC current, a FET is a voltage-controlled device with immense input impedance ($10^8\ \Omega\text{ to }>10^{12}\ \Omega$).

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2. Junction Field Effect Transistors (JFETs)

Construction and Physical Mechanism

An N-channel JFET consists of a bar of N-type silicon with ohmic contacts at each end forming the Source and Drain. Two heavily doped P-type regions ($P^+$) are diffused into opposing sides of the bar and connected together to form the Gate.

N-Channel JFET Biasing:
- Drain is biased positive relative to Source (V_DS > 0)
- Gate is reverse-biased relative to Source (V_GS ≤ 0)

Because the gate-to-channel PN junction is reverse-biased:

1. A depletion region forms and widens into the N-channel.
2. As reverse bias ($|V_{GS}|$) increases, the non-conductive depletion layers expand inward, constricting the cross-sectional area of the conductive N-channel.
3. The narrower channel increases channel resistance, reducing electron flow from source to drain.
4. When reverse gate voltage reaches the Pinch-Off Voltage ($V_P$), the depletion layers touch, pinching off the channel and limiting drain current to a constant saturation value.

Mathematical Formulation: Shockley's Equation

In the active saturation region (where $V_{DS} > |V_P| - |V_{GS}|$), drain current ($I_D$) is governed strictly by gate-source voltage ($V_{GS}$) according to Shockley's Equation:

$I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2$

Where:

• $I_{DSS}$ = Drain-to-Source saturation current with gate shorted to source ($V_{GS} = 0\text{ V}$).
• $V_P$ = Gate-source pinch-off (cutoff) voltage (negative for N-channel, positive for P-channel).
• $V_{GS}$ = Applied gate-to-source reverse bias voltage.

Transconductance ($g_m$)

Because a FET is voltage-controlled, its gain is defined as transconductance ($g_m$), measuring the change in output drain current resulting from a change in input gate voltage:

$g_m = \frac{\Delta I_D}{\Delta V_{GS}} = g_{m0} \left(1 - \frac{V_{GS}}{V_P}\right) \qquad \text{where} \qquad g_{m0} = \frac{2 I_{DSS}}{|V_P|}$

Transconductance is measured in millisiemens (mS) or micromhos ($\mu\text{mho}$).

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3. Metal-Oxide-Semiconductor FETs (MOSFETs)

In a MOSFET, the metallic or polysilicon gate electrode is completely physically isolated from the semiconductor channel by an ultra-thin insulating dielectric layer of silicon dioxide ($SiO_2$):

• Input Impedance: Exceeds $10^{12}\ \Omega$ ($1\text{ T}\Omega$), drawing negligible leakage current (picoamperes).

A. Depletion-Mode MOSFET (D-MOSFET)

A D-MOSFET is fabricated with a physical conducting channel already present between source and drain. It can operate in two distinct modes:

1. Depletion Mode: Applying reverse gate bias ($V_{GS} < 0$ for N-channel) repels channel electrons, depleting the channel and reducing $I_D$.
2. Enhancement Mode: Applying positive gate bias ($V_{GS} > 0$ for N-channel) attracts additional electrons into the channel, enhancing conductivity and increasing $I_D$ above $I_{DSS}$.

B. Enhancement-Mode MOSFET (E-MOSFET)

An E-MOSFET has no physical channel built during fabrication. At zero gate bias ($V_{GS} = 0\text{ V}$), the device is normally-off and no current flows between drain and source ($I_D = 0$).

• Inversion Layer Formation: When a positive gate voltage exceeding the threshold voltage ($V_{GS(th)}$) is applied, the positive electric field repels substrate holes and attracts minority electrons to the $SiO_2$ interface.
• This creates a thin conducting N-type inversion layer bridging the source and drain, turning the transistor ON.
• Significance: E-MOSFETs are the foundation of modern digital avionics: complementary pairs of N-channel and P-channel MOSFETs form CMOS (Complementary MOS) logic gates, which consume virtually zero static power in aircraft computers and FADEC systems.

Electrostatic Discharge (ESD) Hazards

The $SiO_2$ gate insulating layer is sub-microscopically thin (often less than $50\text{ nm}$). Because the dielectric breakdown strength of $SiO_2$ is approximately $10^7\text{ V/cm}$, an electrostatic potential of merely $50\text{ V to }100\text{ V}$ is sufficient to permanently puncture the dielectric barrier, causing catastrophic short-circuit failure.

[!WARNING] ESD Handling in Aircraft Maintenance: Humans routinely accumulate static charges of $3,000\text{ V to }15,000\text{ V}$ simply walking across hangar floors. Handling MOSFETs or CMOS LRU circuit cards without Electrostatic Protected Area (EPA) controls—such as conductive grounded wrist straps with a $1\text{ M}\Omega$ safety resistor, dissipative work mats, and conductive shielding transport bags—will permanently destroy gate insulation or introduce latent gate damage that causes premature in-flight failure.

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4. The Darlington Pair Configuration

When flight computer microcontrollers (supplying only milliampere-level logic outputs) must drive high-current inductive aircraft loads (such as $5\text{ A}$ fuel valves, trim tab motors, or relay solenoids), a single BJT lacks sufficient current gain. The Darlington pair solves this by cascading two bipolar transistors into a single composite device.

Circuit Architecture

• The collectors of both transistors ($Q_1$ and $Q_2$) are tied together.
• The emitter of the input driver transistor ($Q_1$) feeds directly into the base of the main output power transistor ($Q_2$).

Darlington Topology:
      C (Common Collector Node)
      |---------
      |        |
      C1       C2
B --- B1       B2
      E1 ----->|
               E2 --- E (Composite Emitter Node)

Composite Parameters

1. Total Current Gain ($\beta_{total}$): $I_{C1} = \beta_1 I_B \qquad I_{B2} = I_{E1} = (\beta_1 + 1) I_B$ $I_{C2} = \beta_2 I_{B2} = \beta_2 (\beta_1 + 1) I_B$ $I_{C(total)} = I_{C1} + I_{C2} = [\beta_1 + \beta_2 (\beta_1 + 1)] I_B \approx (\beta_1 \cdot \beta_2) I_B$ $\beta_{total} \approx \beta_1 \cdot \beta_2$ If $Q_1$ has $\beta_1 = 100$ and $Q_2$ has $\beta_2 = 50$, the composite gain is $\beta_{total} \approx 5,000$.

2. Composite Input Impedance ($Z_{in}$): $Z_{in} \approx \beta_1 \cdot \beta_2 \cdot R_E$ This extremely high input impedance minimizes loading on preceding control logic.

Engineering Drawbacks & Trade-Offs

1. Double Base-Emitter Drop: $V_{BE(total)} = V_{BE1} + V_{BE2} \approx 0.7\text{ V} + 0.7\text{ V} = 1.4\text{ V}$ The control signal must exceed $1.4\text{ V}$ before conduction can begin.
2. Elevated Saturation Voltage: $V_{CE(sat)} = V_{CE1(sat)} + V_{BE2} \approx 0.2\text{ V} + 0.7\text{ V} = 0.9\text{ V}$ Unlike a single saturated BJT ($V_{CE(sat)} \approx 0.1\text{ to }0.2\text{ V}$), a Darlington cannot saturate below $0.7\text{–}0.9\text{ V}$. At high load currents (e.g., $10\text{ A}$), this causes significant power dissipation ($P = 0.9\text{ V} \times 10\text{ A} = 9.0\text{ W}$), requiring substantial heat sinking.
3. Turn-Off Delay: Trapped base charge in $Q_2$ cannot discharge quickly when $Q_1$ turns off. Practical Darlington devices integrate internal base-emitter "bleed" resistors to speed up turn-off switching.

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Comparison: BJT vs. JFET vs. MOSFET vs. Darlington

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Worked Engineering Calculation: JFET Shockley Operating Point

Problem

An avionics fuel quantity sensor interface employs an N-channel JFET in its preamplifier stage. The manufacturer datasheet specifies:

• Drain saturation current at zero bias: $I_{DSS} = 12.0\text{ mA}$
• Pinch-off voltage: $V_P = -4.0\text{ V}$

If the bias circuit establishes a gate-to-source voltage $V_{GS} = -1.5\text{ V}$, calculate:

1. The quiescent drain current ($I_D$).
2. The zero-bias transconductance ($g_{m0}$).
3. The operating transconductance ($g_m$) at $V_{GS} = -1.5\text{ V}$.

Solution

1. Quiescent Drain Current ($I_D$): Using Shockley's Equation: $I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2 = 12.0\text{ mA} \times \left(1 - \frac{-1.5\text{ V}}{-4.0\text{ V}}\right)^2$ $I_D = 12.0\text{ mA} \times (1 - 0.375)^2 = 12.0\text{ mA} \times (0.625)^2 = 12.0\text{ mA} \times 0.390625 \approx 4.69\text{ mA}$

2. Zero-Bias Transconductance ($g_{m0}$): $g_{m0} = \frac{2 I_{DSS}}{|V_P|} = \frac{2 \times 12.0\text{ mA}}{|-4.0\text{ V}|} = \frac{24.0\text{ mA}}{4.0\text{ V}} = 6.0\text{ mS} = 6000\ \mu\text{S}$

3. Operating Transconductance ($g_m$): $g_m = g_{m0} \left(1 - \frac{V_{GS}}{V_P}\right) = 6.0\text{ mS} \times (1 - 0.375) = 6.0\text{ mS} \times 0.625 = 3.75\text{ mS} = 3750\ \mu\text{S}$ Every $1.0\text{ V}$ change in gate voltage will cause a $3.75\text{ mA}$ change in drain current.