7.4 Logic Circuits, Switching Theory & Microprocessor Systems

7.4 Logic Circuits, Switching Theory & Microprocessor Systems

Topic C of the Engineering Sciences and Allied Subjects TOS (PRBEE Resolution No. 40, s. 2024) is Computer Programming, Microprocessor Systems and Logic Circuits and Switching Theory, weighted 4.5% of the whole examination and 15 of the 100 ESAS items — one of the two largest ESAS topics. The preceding section covered number systems, Boolean algebra fundamentals and structured programming; this section completes the topic with switching-theory minimisation, sequential logic and microprocessor architecture, all of which underpin the PLC and protection-relay logic examined in the professional subject.

---

1. Switching Theory & Boolean Minimisation

De Morgan's Theorems

The two identities that convert between AND and OR forms, and the basis of "bubble pushing":

$\overline{A \cdot B} = \overline{A} + \overline{B} \qquad\qquad \overline{A + B} = \overline{A} \cdot \overline{B}$

Canonical Forms

• Sum of Products (SOP) — an OR of AND terms, one minterm per row where the output is 1;
• Product of Sums (POS) — an AND of OR terms, one maxterm per row where the output is 0.

Karnaugh Map Minimisation

A K-map arranges minterms so that physically adjacent cells differ in exactly one variable (Gray-code ordering). Rules:

1. Group adjacent 1-cells in blocks of $1, 2, 4, 8, \dots$ — powers of two only;
2. Make each group as large as possible; a group of $2^k$ cells eliminates $k$ variables;
3. Groups may overlap and may wrap around the edges of the map;
4. Every 1-cell must be covered at least once; use the fewest groups possible;
5. Don't-care cells ($X$) may be included in a group when doing so enlarges it, or ignored otherwise.

Universal Gates

NAND and NOR are each functionally complete: NOT, AND and OR can all be synthesised from either alone. Because a CMOS NAND is cheaper in silicon than an AND, real integrated logic is overwhelmingly NAND-based.

---

2. Combinational Logic Blocks

---

3. Sequential Logic

The defining distinction: combinational output depends only on present inputs; sequential output depends on present inputs and stored state.

A latch is level-sensitive (transparent while the enable is asserted); a flip-flop is edge-triggered. Confusing the two is a standard distractor.

Cascading $n$ flip-flops produces a counter with $2^n$ states, so a 4-bit counter counts 0–15 and a modulo-10 (decade) counter needs 4 flip-flops with a reset decoded at count 10. A shift register of $n$ stages delays serial data by $n$ clock periods.

Finite state machines come in two flavours: a Moore machine's output depends on the state only; a Mealy machine's output depends on state and current input, so it reacts one clock earlier but is more prone to output glitches.

---

4. Microprocessor Systems

A microprocessor repeats the fetch–decode–execute cycle across three buses:

• Address bus — unidirectional, sets the location; $n$ address lines address $2^n$ locations, so 16 lines reach 64 Ki locations and 20 lines reach 1 Mi;
• Data bus — bidirectional, carries the operand; its width defines the machine's word size;
• Control bus — read/write strobes, interrupt requests, clock and reset.

$\text{Addressable memory} = 2^{(\text{number of address lines})} \text{ locations}$

Key architectural distinctions for the examination:

Microprocessor vs. microcontroller: a microprocessor is a CPU requiring external memory and peripherals; a microcontroller integrates CPU, RAM, ROM/flash, timers and I/O on a single chip — the architecture inside a protective relay, a variable-frequency drive controller or a smart meter.

Interrupts suspend the running program, save the context, execute an interrupt service routine and return. Maskable interrupts can be disabled in software; non-maskable interrupts (used for power-fail detection in substation IEDs) cannot. Polling, by contrast, wastes processor time continuously checking a flag.

---

Solved Board Exam Examples

Example 1: Boolean Simplification

Simplify $Y = A\overline{B} + AB + \overline{A}B$.

Solution. Combine the first two terms, which differ only in $B$:

$A\overline{B} + AB = A(\overline{B} + B) = A(1) = A$

$Y = A + \overline{A}B$

Applying the absorption identity $X + \overline{X}Y = X + Y$:

$Y = \boxed{A + B}$

The function is simply OR — three product terms collapse to one two-input gate.

Example 2: Address Bus Sizing

A microcontroller must address 256 KiB of memory. How many address lines are required?

Solution. $256 \text{ KiB} = 256 \times 1024 = 262,144 = 2^{18}$ bytes.

$n = \log_{2}(2^{18}) = \boxed{18 \text{ address lines}}$

Sixteen lines would reach only 64 KiB, and 20 lines would reach 1 MiB — both are supplied as distractors.

Example 3: Decade Counter Flip-Flop Count

How many flip-flops are needed for a modulo-10 (BCD decade) counter?

Solution. The counter must represent ten distinct states, 0 through 9, so we need the smallest $n$ satisfying $2^n \ge 10$. Since $2^3 = 8 < 10$ and $2^4 = 16 \ge 10$, the answer is $\boxed{4 \text{ flip-flops}}$, with the unused states 10–15 decoded to force a synchronous reset back to zero.