7.3 Computer Fundamentals, Programming & Data Logic

Key Takeaways

  • Von Neumann architecture comprises CPU (ALU, CU, Registers), memory unit (RAM/ROM), and I/O interface connected via system buses.
  • Signed integers use 2's complement representation with range $[-2^{n-1}, 2^{n-1}-1]$; IEEE 754 single precision stores 32-bit floats using 1 sign bit, 8 exponent bits, and 23 mantissa bits.
  • De Morgan's Laws ($\\overline{A+B} = \\bar{A}\\cdot\\bar{B}$ and $\\overline{A\\cdot B} = \\bar{A} + \\bar{B}$) and Karnaugh maps simplify Boolean logic expressions for digital hardware design.
  • High-level programming utilizes control flow constructs (sequence, selection, iteration) and modular functions to execute algorithm logic efficiently.
  • Computer networks utilize the 7-layer OSI model and IPv4/IPv6 addressing to structure digital communications.
Last updated: August 2026

7.3 Computer Fundamentals, Programming & Data Logic

Computer Fundamentals and Computer Programming constitute a dedicated portion of the ESAS subject area in the REE Licensure Examination. Electrical engineers regularly interface with microcontrollers, PLCs, embedded control systems, digital signal processors, and software algorithms.


1. Computer Hardware & Systems Architecture

The Von Neumann Architecture

Most modern computing systems are based on the Von Neumann Architecture, which features stored programs where instructions and data share the same memory space.

                  VON NEUMANN SYSTEM ARCHITECTURE
  ┌─────────────────────────────────────────────────────────────┐
  │                 CENTRAL PROCESSING UNIT (CPU)               │
  │  ┌─────────────────────────┐   ┌─────────────────────────┐  │
  │  │ Arithmetic Logic Unit   │   │      Control Unit       │  │
  │  │        (ALU)            │   │          (CU)           │  │
  │  └────────────┬────────────┘   └────────────┬────────────┘  │
  │               │    ┌───────────────────┐    │               │
  │               └───►│ CPU Registers (PC,│◄───┘               │
  │                    │ IR, MAR, MDR, ACC)│                    │
  │                    └───────────────────┘                    │
  └──────────────────────────────┬──────────────────────────────┘
                                 │ System Bus (Data, Address, Control)
  ┌──────────────────────────────┴──────────────────────────────┐
  │                     MAIN MEMORY (RAM / ROM)                 │
  └──────────────────────────────┬──────────────────────────────┘
                                 │ I/O Bus
  ┌──────────────────────────────┴──────────────────────────────┐
  │                 INPUT / OUTPUT (I/O) DEVICES                │
  └─────────────────────────────────────────────────────────────┘

Key CPU Components & Memory Hierarchy

  • Arithmetic Logic Unit (ALU): Performs integer arithmetic (add, subtract) and bitwise logical operations (AND, OR, XOR, shift).
  • Control Unit (CU): Fetches instructions from memory, decodes operation codes, and generates timing signals.
  • Registers: High-speed storage inside CPU (e.g., Program Counter PC, Instruction Register IR, Accumulator ACC).
  • Memory Hierarchy: Registers (Fastest/Smallest) $\rightarrow$ L1/L2/L3 Cache $\rightarrow$ Main Memory (RAM) $\rightarrow$ Secondary Storage (NVMe/SSD/HDD) (Slowest/Largest).

2. Number Systems & Data Representation

Positional Radix Systems

Number SystemRadix (Base)Valid Digits / SymbolsExample Representation
Binary20, 1$1011.01_2$
Octal80, 1, 2, 3, 4, 5, 6, 7$15.2_8$
Decimal100, 1, 2, 3, 4, 5, 6, 7, 8, 9$11.25_{10}$
Hexadecimal160–9, A(10), B(11), C(12), D(13), E(14), F(15)$\text{B}.4_{16}$

2's Complement Signed Integer Representation

To represent negative integers in binary using $n$ bits:

  1. Write the $n$-bit magnitude binary representation of the positive number.
  2. Invert all bits ($0 \rightarrow 1$ and $1 \rightarrow 0$) to form the 1's complement.
  3. Add 1 to the 1's complement to yield the 2's complement.
  • Representable Range for $n$ bits: $-2^{n-1} \le X \le 2^{n-1} - 1$
    • For 8 bits ($n=8$): Range is $-128$ to $+127$.
    • For 16 bits ($n=16$): Range is $-32,768$ to $+32,767$.

IEEE 754 Floating-Point Standard (Single Precision 32-bit)

Value=(1)S×1.M×2E127\text{Value} = (-1)^S \times 1.M \times 2^{E - 127}

  • Sign Bit ($S$): Bit 31 (1 bit, 0 = Positive, 1 = Negative)
  • Biased Exponent ($E$): Bits 30–23 (8 bits, Bias = 127)
  • Mantissa / Significand ($M$): Bits 22–0 (23 bits, implicit leading 1)

3. Boolean Algebra & Logic Gates

Digital logic circuits implement Boolean functions using basic and universal logic gates.

Basic Logic Gate Summary

Gate TypeBoolean ExpressionTruth Table Output ($A, B$)Note
AND$Y = A \cdot B$1 only if $A=1$ AND $B=1$Series contacts
OR$Y = A + B$1 if $A=1$ OR $B=1$Parallel contacts
NOT$Y = \bar{A}$Inverts input bitInverter
NAND$Y = \overline{A \cdot B}$0 only if $A=1$ AND $B=1$Universal Gate
NOR$Y = \overline{A + B}$1 only if $A=0$ AND $B=0$Universal Gate
XOR$Y = A \oplus B = A\bar{B} + \bar{A}B$1 if inputs are DIFFERENTOdd parity check
XNOR$Y = \overline{A \oplus B} = AB + \bar{A}\bar{B}$1 if inputs are EQUALEquivalence check

Key Boolean Algebra Laws

  • De Morgan's First Law: $\overline{A + B} = \bar{A} \cdot \bar{B}$
  • De Morgan's Second Law: $\overline{A \cdot B} = \bar{A} + \bar{B}$
  • Absorption Law: $A + (A \cdot B) = A \quad \text{and} \quad A \cdot (A + B) = A$
  • Consensus Theorem: $A B + \bar{A} C + B C = A B + \bar{A} C$

4. Structured Programming & Algorithm Logic

Control Flow Structures

High-level languages (such as C, C++, Python) structure execution logic into three fundamental patterns:

  1. Sequence: Step-by-step execution of linear statements.
  2. Selection (Branching): Decision-making via if-else or switch-case statements based on conditional boolean evaluation.
  3. Iteration (Looping): Repeating code blocks via for, while, or do-while constructs.

OSI 7-Layer Networking Reference Model

LayerLayer NameCore Function / Protocol
7ApplicationHTTP, HTTPS, FTP, SMTP, DNS
6PresentationData encryption, SSL/TLS, compression, ASCII encoding
5SessionSession establishment, management, teardown (RPC, NetBIOS)
4TransportEnd-to-end reliability, port addressing, TCP (connection-oriented), UDP
3NetworkLogical IP addressing, packet routing (IPv4, IPv6, ICMP, Routers)
2Data LinkPhysical MAC addressing, framing, error detection (Ethernet, Switches)
1PhysicalTransmission of raw bit streams over physical medium (Cables, Fiber, Hubs)

Solved Practice Examples

Example 1: 2's Complement Conversion

Problem: Find the 8-bit 2's complement binary representation of the decimal integer $-43_{10}$.

Solution:

  1. Write positive magnitude $+43_{10}$ in 8-bit binary: +4310=001010112+43_{10} = 00101011_2
  2. Take the 1's complement (invert all bits): 1’s Comp=110101002\text{1's Comp} = 11010100_2
  3. Add 1 to obtain 2's complement: 2’s Comp=110101002+12=110101012\text{2's Comp} = 11010100_2 + 1_2 = 11010101_2 Thus, $-43_{10} = 11010101_2$.

Example 2: Boolean Expression Simplification

Problem: Simplify the Boolean expression $Y = A B C + A B \bar{C} + A \bar{B} C$.

Solution:

  1. Factor out $AB$ from the first two terms: Y=AB(C+Cˉ)+ABˉCY = A B (C + \bar{C}) + A \bar{B} C
  2. Apply inverse law $C + \bar{C} = 1$: Y=AB(1)+ABˉC=AB+ABˉCY = A B (1) + A \bar{B} C = A B + A \bar{B} C
  3. Factor out $A$ from remaining terms: Y=A(B+BˉC)Y = A (B + \bar{B} C)
  4. Apply distributive law $B + \bar{B} C = (B + \bar{B})(B + C) = 1 \cdot (B + C)$: Y=A(B+C)=AB+ACY = A (B + C) = A B + A C
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OSI 7-Layer Network Architecture Model
Relative Access Latency (Arbitrary Units / Nanoseconds) Across Computer Memory Hierarchy
Test Your Knowledge

What is the decimal equivalent of the 8-bit signed binary number $11110100_2$ represented in 2's complement format?

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B
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Test Your Knowledge

Which Boolean algebra theorem is represented by the equivalence $\overline{X \cdot Y} = \bar{X} + \bar{Y}$?

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B
C
D
Test Your Knowledge

In the 7-layer OSI networking reference model, which layer is responsible for logical IP addressing, packet routing, and subnet management?

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B
C
D