8.2 FET Characteristics, Biasing & Amplifier Circuits

8.2 FET Characteristics, Biasing & Amplifier Circuits

1. FET Physical Fundamentals & Device Classification

Field-Effect Transistors (FETs) are voltage-controlled, unipolar semiconductor devices in which conduction occurs purely via majority charge carriers (electrons in N-channel, holes in P-channel). Because the gate terminal is reverse-biased or insulated by silicon dioxide ($SiO_2$), input impedance is extremely high ($10^8\ \Omega$ for JFETs, up to $10^{14}\ \Omega$ for MOSFETs).

Classification of Field-Effect Transistors

1. Junction Field-Effect Transistors (JFET): Reverse-biased $pn$ junction controls depletion region width and channel cross-sectional area.
2. Depletion-Mode MOSFET (D-MOSFET): Built with a physical channel; can operate in depletion mode ($V_{GS} < 0$) or enhancement mode ($V_{GS} > 0$).
3. Enhancement-Mode MOSFET (E-MOSFET): No physical channel at $V_{GS} = 0\text{ V}$. An inversion layer channel is induced when $V_{GS}$ exceeds threshold voltage $V_{Th}$.

BJT vs. FET Comparison

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2. FET Transfer Characteristics & Mathematical Equations

A. Shockley's Equation (JFET & D-MOSFET)

In the saturation (pinch-off/active) region where $V_{DS} \ge |V_{GS} - V_P|$:

$$I_D = I_{DSS} \left( 1 - \frac{V_{GS}}{V_P} \right)^2$$

Where:

• $I_{DSS}$: Drain-to-source saturation current when $V_{GS} = 0\text{ V}$.
• $V_P$ (or $V_{GS(off)}$): Pinch-off voltage at which $I_D = 0\text{ A}$. For N-channel JFET, $V_P$ is negative.

B. E-MOSFET Saturation Current Equation

For $V_{GS} > V_{Th}$ and $V_{DS} \ge V_{GS} - V_{Th}$:

$$I_D = k (V_{GS} - V_{Th})^2$$

Where constant $k$ is given by:

$$k = \frac{I_{D(on)}}{(V_{GS(on)} - V_{Th})^2} = \frac{1}{2} \mu_n C_{ox} \left(\frac{W}{L}\right)$$

C. Transconductance ($g_m$)

Transconductance quantifies the control of gate voltage over drain current:

$$g_m = \frac{\partial I_D}{\partial V_{GS}}$$

• For JFETs & D-MOSFETs:

$$g_m = g_{m0} \left( 1 - \frac{V_{GS}}{V_P} \right) = \frac{2 \sqrt{I_{DSS} I_D}}{|V_P|}$$

Where maximum transconductance at $V_{GS} = 0\text{ V}$ is:

$$g_{m0} = \frac{2 I_{DSS}}{|V_P|}$$

• For E-MOSFETs:

$$g_m = 2 k (V_{GS} - V_{Th}) = 2 \sqrt{k I_D}$$

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3. FET DC Biasing Circuits

A. Self-Bias Circuit (JFET & D-MOSFET)

• Gate is referenced to ground via high resistor $R_G$ ($I_G = 0\text{ A} \implies V_G = 0\text{ V}$).
• Gate-Source Bias Voltage:

$$V_{GS} = -I_D R_S$$

• Combining with Shockley's equation yields a quadratic equation in $I_D$:

$$I_D = I_{DSS} \left( 1 + \frac{I_D R_S}{V_P} \right)^2$$

• Drain-Source Voltage:

$$V_{DS} = V_{DD} - I_D(R_D + R_S)$$

B. Voltage-Divider Bias Circuit

• Gate Voltage:

$$V_G = V_{DD} \cdot \frac{R_2}{R_1 + R_2}$$

• Gate-Source Voltage:

$$V_{GS} = V_G - I_D R_S$$

• Solved algebraically or graphically by intersecting the bias line $V_{GS} = V_G - I_D R_S$ with the Shockley transfer curve.

C. Drain-Feedback Bias (E-MOSFET)

• Resistor $R_G$ connected between Drain and Gate ($I_G = 0 \implies V_{GS} = V_{DS}$):

$$V_{GS} = V_{DS} = V_{DD} - I_D R_D$$

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4. Small-Signal AC FET Amplifiers

In AC equivalent models, the FET is modeled as a voltage-controlled current source $g_m v_{gs}$ in parallel with drain resistance $r_d = \frac{1}{y_{os}}$.

A. Common Source (CS) Amplifier (Bypassed $R_S$)

• Input Impedance: $Z_{in} = R_G$
• Output Impedance: $Z_{out} = R_D \parallel r_d \approx R_D$
• No-Load Voltage Gain: $A_v = -g_m (R_D \parallel r_d) \approx -g_m R_D$
• Loaded Voltage Gain: $A_{vL} = -g_m (R_D \parallel R_L)$
• Phase Relationship: $180^\circ$ phase inversion.

B. Common Source with Unbypassed Source Resistor ($R_S$)

• Voltage Gain: $A_v = -\frac{g_m (R_D \parallel R_L)}{1 + g_m R_S}$
• Benefit: Degenerative feedback stabilizes gain against $g_m$ variations.

C. Common Drain (CD) / Source Follower

• Input Impedance: $Z_{in} = R_G$
• Output Impedance: $Z_{out} = R_S \parallel \frac{1}{g_m}$
• Voltage Gain: $A_v = \frac{g_m (R_S \parallel R_L)}{1 + g_m (R_S \parallel R_L)} \approx +1$
• Phase Relationship: $0^\circ$ phase shift.
• Primary Application: High-input impedance buffer.

D. Common Gate (CG) Amplifier

• Input Impedance: $Z_{in} = R_S \parallel \frac{1}{g_m} \approx \frac{1}{g_m}$ (Low, e.g., $100-500\ \Omega$)
• Output Impedance: $Z_{out} = R_D$
• Voltage Gain: $A_v = +g_m (R_D \parallel R_L)$
• Phase Relationship: $0^\circ$ phase shift.