9.3 Sequential Logic, Flip-Flops & Microprocessor Architecture

9.3 Sequential Logic, Flip-Flops & Microprocessor Architecture

Quick Answer: Sequential logic circuits rely on memory elements (flip-flops) where current output depends on present inputs and previous internal state. The JK flip-flop toggles (Q_{next} = NOT(Q)) when J=K=1, solving the SR invalid state. n-bit counters achieve a maximum modulus MOD = 2ⁿ. Microprocessor systems use unidirectional address buses, bidirectional data buses, and control buses to interface with memory and I/O. The 8-bit Intel 8085 addresses 64 KB (16-bit address bus), while the 16-bit Intel 8086 uses a 20-bit address bus to access 1 MB of segmented memory decoded via address decoders like the 74LS138.

1. Latches vs. Flip-Flops & Excitation Characteristics

Unlike combinational logic, sequential logic circuits contain memory elements. A latch is an asynchronous level-sensitive storage element, whereas a flip-flop is a clock-edge-triggered bistable multivibrator.

Primary Flip-Flop Types & Characteristic Equations

1. SR (Set-Reset) Flip-Flop:
   • Characteristic Equation: Q_{next} = S + NOT(R)Q (Condition: S · R = 0)
   • Invalid State: S=1, R=1 results in unpredictable output states and must be prohibited.
2. JK Flip-Flop:
   • Characteristic Equation: Q_{next} = J NOT(Q) + NOT(K)Q
   • Toggles output (Q_{next} = NOT(Q)) when J=1, K=1. Master-Slave configurations or edge-triggering eliminate race-around conditions when clock pulse width exceeds flip-flop propagation delay.
3. D (Data/Delay) Flip-Flop:
   • Characteristic Equation: Q_{next} = D
   • Formed by connecting J=D and K=NOT(D) on a JK flip-flop. Transfers input D to output Q on the active clock edge.
4. T (Toggle) Flip-Flop:
   • Characteristic Equation: Q_{next} = T ⊕ Q = T NOT(Q) + NOT(T)Q
   • Formed by tying J=K=T. Toggles when T=1, holds state when T=0. Used extensively in binary frequency division and counters.

Flip-Flop Excitation Table

The excitation table dictates the required input conditions to force a transition from present state Q to next state Q_{next}:

(X represents a Don't Care condition).

Timing Constraints

• Setup Time (t_{su}): Minimum duration input signals must remain stable before the active clock edge.
• Hold Time (t_h): Minimum duration input signals must remain stable after the active clock edge.

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2. Counters & Shift Registers

Asynchronous (Ripple) vs. Synchronous Counters

• Asynchronous (Ripple) Counters: The output of each flip-flop drives the clock input of the next stage. Ripple counters suffer from accumulated propagation delay (t_{total} = n · t_{pd}), limiting maximum operating frequency.
• Synchronous Counters: All flip-flops are tied to a common global clock signal, triggering simultaneously. Logic gates determine next-state excitation, eliminating ripple accumulation.

Counter Modulus & Mod-N Design

The Modulus (MOD) of a counter is the total number of unique states it cycles through before repeating.

• An n-bit binary counter has a maximum modulus of MOD = 2ⁿ.
• Truncated MOD-N Counters: To design a counter with MOD = N < 2ⁿ, a NAND gate detects count N in binary and asserts active-low asynchronous NOT(CLEAR) inputs on all flip-flops, resetting the count to 0.

Shift Register Classifications

Shift registers consist of cascaded D or JK flip-flops that move data bits by one position per clock pulse.

1. SISO (Serial-In, Serial-Out): Converts serial data into delayed serial data.
2. SIPO (Serial-In, Parallel-Out): Converts serial input into n-bit parallel data words.
3. PISO (Parallel-In, Serial-Out): Loads n-bit parallel data simultaneously and shifts out serially.
4. PIPO (Parallel-In, Parallel-Out): Functions as a multi-bit memory buffer register.
5. Special Shift Counters:
   • Ring Counter: Connects the output of the last flip-flop directly to the first (Q_n → D₀). An n-bit Ring counter has N = n states.
   • Johnson (Twisted Ring) Counter: Connects inverted output of last flip-flop to first (NOT(Q_n) → D₀). An n-bit Johnson counter yields N = 2n states.

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3. Microprocessor Architecture: Intel 8085 & 8086

Bus Structure Principles

Microprocessor systems communicate with memory and peripheral devices over three primary system buses:

1. Address Bus: Unidirectional. Carries memory or I/O address location coordinates from CPU to external chips.
2. Data Bus: Bidirectional. Transfers instructions and data between CPU, memory, and peripheral devices.
3. Control Bus: Contains individual control lines (NOT(RD), NOT(WR), M/NOT(IO), ALE) that dictate timing and operation direction.

       +-------------------------------------------------+
       |          Intel Microprocessor (CPU)             |
       +-------+-------------------+-----------------+---+
               |                   |                 |
  Address Bus  | (Unidirectional)  | Data Bus        | Control Bus
  =============>                   <=================> =============>
               |                   |                 |
       +-------v-------------------v-----------------v---+
       |       System Memory (SRAM / DRAM / EPROM)       |
       +-------------------------------------------------+

Intel 8085 Microprocessor (8-bit)

• Data Bus Width: 8 bits (D₀ - D₇).
• Address Bus Width: 16 bits (A₀ - A₁₅), providing an addressable memory range of 2¹⁶ = 65,536 bytes (64 KB). Lower address lines are multiplexed with data lines (AD₀ - AD₇) to save pin count, demultiplexed using an external latch (74LS373) triggered by Address Latch Enable (ALE).
• Internal Registers: Accumulator (A), Flags, general-purpose registers (B, C, D, E, H, L paired as BC, DE, HL), 16-bit Program Counter (PC), and 16-bit Stack Pointer (SP).

Intel 8086 Microprocessor (16-bit)

• Data Bus Width: 16 bits (D₀ - D₁₅).
• Address Bus Width: 20 bits (A₀ - A₁₉), expanding addressable physical memory to 2²⁰ = 1,048,576 bytes (1 MB).
• Internal Architecture: Divided into two parallel processing units:
  1. Bus Interface Unit (BIU): Fetches instructions, handles memory address calculations, and maintains a 6-byte instruction prefetch queue.
  2. Execution Unit (EU): Decodes and executes instructions using the 16-bit ALU and register set.
• Memory Segmentation: The 1 MB memory space is divided into logical segments of 64 KB each. Physical addresses are computed by shifting a 16-bit Segment Register left by 4 bits (16₁₀) and adding a 16-bit Offset Register: $\text{Physical Address} = (\text{Segment Register} \times 16_{10}) + \text{Offset}$
  • Code Segment (CS:IP), Data Segment (DS:SI), Stack Segment (SS:SP), Extra Segment (ES:DI).

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4. Memory Systems & Address Decoding

Computer memory consists of Read-Only Memory (ROM - non-volatile instruction storage) and Random-Access Memory (RAM - volatile read/write workspace).

Address Decoding Techniques

To prevent memory bus contention, each memory IC is assigned a unique address range using decoding circuitry to activate the chip's active-low Chip Select (NOT(CS)) or Chip Enable (NOT(CE)) input.

• High-order address lines (A₁₅-A₁₃ in 8085) connect to decoder inputs (e.g., 3-to-8 Decoder 74LS138), while low-order address lines (A₁₂-A₀) connect directly to memory IC address pins.
• Example Calculation: Connecting A₁₅, A₁₄, A₁₃ to a 74LS138 decoder divides 64 KB into eight 8 KB blocks (8192 bytes per NOT(CS) output). Output NOT(Y₀) activates for address range 0000H to 1FFFH, NOT(Y₁) for 2000H to 3FFFH, and so forth.