9.2 Boolean Algebra, Logic Gates & Combinational Circuits

9.2 Boolean Algebra, Logic Gates & Combinational Circuits

Quick Answer: Combinational logic circuits evaluate Boolean expressions where output states depend strictly on present inputs. Boolean algebra optimization leverages identity rules, consensus theorems, and De Morgan's laws (NOT(A · B) = NOT(A) + NOT(B)). Karnaugh mapping minimizes logic functions by grouping adjacent 1s in Gray-code p-subspaces of size 2ᵏ. NAND and NOR gates are universal building blocks capable of implementing any logic function. Standard modular combinational sub-systems include 2ⁿ-to-1 Multiplexers (MUX), n-to-2ⁿ Decoders, Priority Encoders, and binary Adders (Half Adder and Full Adder).

1. Boolean Algebra Theorems & Laws

Digital logic operates on binary variables restricted to two states: 0 (FALSE/LOW) and 1 (TRUE/HIGH). Boolean algebra establishes the formal mathematical rules for manipulating binary logic functions.

Core Axioms and Single-Variable Theorems

• Identity Laws: A · 1 = A, A + 0 = A
• Null (Nullity) Laws: A · 0 = 0, A + 1 = 1
• Idempotent Laws: A · A = A, A + A = A
• Complementarity Laws: A · NOT(A) = 0, A + NOT(A) = 1
• Involution Law: NOT(NOT(A)) = A

Multi-Variable Theorems & De Morgan's Laws

• Commutative Laws: A · B = B · A, A + B = B + A
• Associative Laws: (A · B) · C = A · (B · C), (A + B) + C = A + (B + C)
• Distributive Laws: A · (B + C) = AB + AC, A + (B · C) = (A + B)(A + C)
• Absorption Laws: A + AB = A, A(A + B) = A, A + NOT(A)B = A + B
• Consensus Theorem: AB + NOT(A)C + BC = AB + NOT(A)C
• De Morgan's First Law: The complement of a product equals the sum of the complements: $$\overline{A \cdot B} = \overline{A} + \overline{B}$$
• De Morgan's Second Law: The complement of a sum equals the product of the complements: $$\overline{A + B} = \overline{A} \cdot \overline{B}$$

De Morgan's laws allow engineers to convert Sum-of-Products (SOP) expressions directly into all-NAND implementations and Product-of-Sums (POS) expressions into all-NOR implementations.

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2. Logic Gate Truth Tables & Universal Logic

Logic gates are physical electronic hardware devices that execute primitive Boolean operations.

Standard Primitive Gates

The primitive logic gates and their governing truth table definitions are summarized below:

Note: Exclusive-OR (XOR) output Y = A NOT(B) + NOT(A) B yields 1 if and only if an odd number of inputs are 1. XNOR Y = AB + NOT(A)NOT(B) acts as a 2-bit equality comparator.

Universal Gate Synthesis (NAND & NOR)

NAND and NOR gates are termed universal gates because any digital logic expression can be implemented using only one type of these gates.

1. NOT Function using NAND: Connect both inputs together: Y = NOT(A · A) = NOT(A).
2. AND Function using NAND: Cascade a NAND gate with an inverting NAND gate: Y = NOT(NOT(A · B)) = A · B.
3. OR Function using NAND: Invert inputs individually and apply to a NAND gate: Y = NOT(NOT(A) · NOT(B)) = A + B (via De Morgan).

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3. Karnaugh Map (K-Map) Minimization & Quine-McCluskey Method

Graphical minimization of Boolean expressions up to 4 variables relies on Karnaugh Maps (K-maps). A K-map organizes minterms into a multidimensional grid where adjacent cells differ by exactly one binary digit (Gray code ordering: 00, 01, 11, 10).

K-Map Grouping Rules

To minimize a Sum-of-Products (SOP) function F(A,B,C,D):

1. Plot 1s for each minterm in the function truth table.
2. Group adjacent 1s into rectangular blocks whose size is a power of 2 (1, 2, 4, 8, 16).
3. Groups must be as large as possible. Larger groups eliminate more variables.
4. Wrap-around grouping is valid: top and bottom edges are adjacent, as are left and right edges.
5. Don't Care (X) Conditions: Inputs that cannot occur or whose output is irrelevant can be treated as 1 if it aids in forming a larger group, or 0 otherwise.

Worked Example: 4-Variable K-Map Minimization

Consider the Boolean function:

$$F(A,B,C,D) = \sum m(2, 3, 6, 7, 8, 10, 12, 14)$$

Let's lay out the 4x4 grid with rows AB (00, 01, 11, 10) and columns CD (00, 01, 11, 10):

• Minterms 2, 3, 6, 7 fill the 2nd row (AB=00,01 with CD=10,11), forming a quad group covering C=1, D=don't care, A=0. Group 1 yield: NOT(A)C.
• Minterms 8, 10, 12, 14 occupy AB=10, 11 with D=0 (CD=00, 10). The 4 corners/column-10 form a quad group yielding: A NOT(D).
• Combining these prime implicants results in the minimal SOP expression: $$F_{min} = \overline{A}C + A\overline{D}$$

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4. Standard Combinational Logic Sub-systems

Multiplexers (Data Selectors)

A Multiplexer (MUX) routes data from one of N = 2ⁿ input lines to a single output line based on n select control lines.

• 4-to-1 MUX: Features 4 data inputs (I₀, I₁, I₂, I₃), 2 select lines (S₁, S₀), and output Y: $$Y = \overline{S_1}\overline{S_0}I_0 + \overline{S_1}S_0 I_1 + S_1\overline{S_0}I_2 + S_1 S_0 I_3$$
• Universal Function Generator: An N-to-1 MUX can directly implement any n-variable Boolean function by applying the variables to the n select lines and tying the data inputs I_k to logic 0, logic 1, or the (n+1)-th variable.

Decoders & Encoders

• Decoder (n-to-2ⁿ): Converts an n-bit binary input code into 2ⁿ unique output lines, where exactly one output line is activated at a time. A 3-to-8 decoder (e.g., IC 74LS138) with active-low enable lines generates all 8 canonical minterms for inputs (A, B, C).
• Priority Encoder (2ⁿ-to-n): Performs the reverse operation of a decoder, converting the highest-order active input line into its corresponding binary representation (e.g., 8-to-3 priority encoder 74LS148).

Binary Arithmetic Circuits

• Half Adder: Adds two 1-bit inputs (A, B) producing a Sum (S) and Carry-out (C): $$S = A \oplus B, \quad C = A \cdot B$$
• Full Adder: Adds two 1-bit inputs (A, B) plus an incoming Carry-in (C_{in}): $$S = A \oplus B \oplus C_{in}$$ $$C_{out} = AB + C_{in}(A \oplus B) = AB + BC_{in} + AC_{in}$$
• Ripple-Carry Adder: Cascades n Full Adders in series to add n-bit binary numbers. The total propagation delay is limited by carry propagation through all n stages (t_{delay} = n · t_{carry}). Carry-Lookahead Adders (CLA) eliminate this bottleneck by calculating carry signals in parallel using generate (G_i = A_i B_i) and propagate (P_i = A_i ⊕ B_i) logic.