5.3 Sequential Logic, Flip-Flops, Counters, and Displays

5.3 Sequential Logic, Flip-Flops, Counters, and Displays

While combinational logic gates process inputs instantaneously, modern aircraft computers require memory elements to store data, count events, synchronize data transfers, and drive flight deck instrumentation. Sequential logic circuits incorporate feedback paths and storage components whose output states depend on both current inputs and previous operational history. This section details bistable multivibrators (SR, D, and JK flip-flops), synchronous and asynchronous binary counters, and 7-segment display decoder interfaces used in avionics systems.

Fundamentals of Sequential Logic and Clocking

The fundamental building block of sequential logic is the bistable multivibrator (flip-flop or latch), a circuit capable of remaining indefinitely in one of two stable voltage states (Logic 0 or Logic 1) until triggered by an external input signal.

Sequential circuits are governed by clock signals:

• Level-Triggered Latches: Change output states whenever the clock input is held at a specific continuous voltage level (High or Low).
• Edge-Triggered Flip-Flops: Sample input data and update output states exclusively during a rapid clock voltage transition. A positive-edge triggered flip-flop responds on the rising edge ($\uparrow$, 0 to 1), whereas a negative-edge triggered flip-flop responds on the falling edge ($\downarrow$, 1 to 0).

Flip-Flop Architectures

1. Set-Reset (SR) Flip-Flop

The SR flip-flop possesses two control inputs: $S$ (Set) and $R$ (Reset).

• When $S=1$ and $R=0$, the output $Q$ sets to 1.
• When $S=0$ and $R=1$, the output $Q$ resets to 0.
• When $S=0$ and $R=0$, the output $Q$ holds its previous state ($Q_n$).
• When $S=1$ and $R=1$, an invalid (forbidden) state occurs. Both outputs $Q$ and $\bar{Q}$ attempt to drive Low simultaneously, causing unpredictable outputs and race conditions when inputs transition back to 0.

2. Data (D) Flip-Flop

The D flip-flop resolves the SR invalid state by routing a single Data input ($D$) to the Set input while feeding an inverted version ($\bar{D}$) to the Reset input.

• On the active clock transition, output $Q$ assumes the exact logic value present at input $D$ ($Q_{n+1} = D$).
• D flip-flops serve as 1-bit storage cells in data registers, buffer latches, and serial-to-parallel shift registers within ARINC 429 bus receiver ICs.

3. Jack-Kilby (JK) Flip-Flop

The JK flip-flop is a versatile, universal flip-flop that completely eliminates the invalid condition of the SR flip-flop.

• When $J=0$ and $K=0$, the output holds its state ($Q_{n+1} = Q_n$).
• When $J=1$ and $K=0$, output $Q$ sets to 1.
• When $J=0$ and $K=1$, output $Q$ resets to 0.
• When $J=1$ and $K=1$, the flip-flop enters Toggle Mode ($Q_{n+1} = \bar{Q}_n$). On every active clock pulse, the output inverts to its opposite state.

In level-triggered JK circuits, holding $J=1$ and $K=1$ while the clock remains High causes continuous uncontrolled output toggling (race-around condition). Master-Slave or edge-triggered internal structures prevent race-around by sampling inputs during the rising clock edge and latching outputs on the falling edge.

Binary Counters: Asynchronous vs. Synchronous

Digital counters consist of cascaded flip-flops configured to count clock pulses, divide frequencies, or measure time intervals in flight control systems.

Asynchronous (Ripple) Counters

In an asynchronous (ripple) counter, only the first flip-flop receives the master external clock signal. Each subsequent flip-flop is clocked by the output ($Q$ or $\bar{Q}$) of the preceding stage.

• Advantage: Simple circuit design requiring minimal logic gating.
• Disadvantage: Cumulative Propagation Delay. Each flip-flop introduces an internal propagation delay ($t_{pd}$). For an $N$-stage counter, the total delay before the final bit settles is $t_{\text{total}} = N \times t_{pd}$.
• At high clock frequencies, this cumulative delay causes intermediate output state decoding errors ("glitches"). Consequently, ripple counters are restricted to low-frequency timing applications in avionics.

Synchronous Counters

In a synchronous counter, the master clock signal is connected in parallel to the clock inputs of all flip-flops simultaneously. Logic gates process the $Q$ outputs to drive the $J$ and $K$ enable inputs of subsequent stages.

• Advantage: All output bits toggle at the exact same instant, eliminating cumulative propagation delay skew.
• Application: Synchronous counters are mandatory for high-speed avionics timing generators, master clock dividers, and digital tachometer systems.

7-Segment Decoders and Cockpit Display Drivers

7-segment displays arrange seven individual light-emitting diode (LED) or liquid crystal display (LCD) segments (labeled $a, b, c, d, e, f, g$) in a figure-8 pattern to form digits 0 through 9.

Decoder/Driver Integrated Circuits

Decoder ICs (such as the 74LS47 or 74HC4511) accept 4-bit Binary Coded Decimal (BCD) input lines ($D, C, B, A$) and decode them into 7 distinct output lines to energize the correct display segments.

Display Electrical Configurations

1. Common Anode Display: The positive anodes of all seven segment LEDs are tied together to $+V_{CC}$. To illuminate a segment, the decoder output connected to that segment's cathode must drive Low ($0\text{V}$) to sink current. Common Anode displays require active-low decoder outputs (such as the 74LS47).
2. Common Cathode Display: The negative cathodes of all seven segment LEDs are tied together to Ground ($0\text{V}$). To illuminate a segment, the decoder output must drive High ($+5\text{V}$) to source current. Common Cathode displays require active-high decoder outputs (such as the 74HC4511).

Flip-Flop Operational Characteristics Summary

Avionics Technical Traps & Exam Watch

• Ripple Counter Glitch Trap: Attempting to decode intermediate counter states from an asynchronous ripple counter while it is counting at high frequencies will lead to spurious control pulses. Technicians diagnosing erratic system resets must check if high-speed logic is improperly driven by a ripple counter rather than a synchronous counter.
• Decoder-Display Polarity Mismatch Trap: Connecting an active-low decoder IC (74LS47 designed for Common Anode displays) to a Common Cathode display causes inverted display behavior: segments that should be dark will illuminate, and segments that should be lit will turn off, displaying corrupted visual symbols.