5.2 Logic Gates and Logic Families

5.2 Logic Gates and Logic Families

Digital flight control, engine monitoring, and warning systems rely on logic gates to process discrete signals from cockpit switches, sensor relays, and microprocessors. A logic gate is a physical electronic circuit that performs a specific boolean algebraic operation on one or more binary inputs to produce a single binary output. This section covers fundamental logic gate operations, De Morgan's algebraic laws, positive versus negative logic conventions, and the electrical operating parameters of Transistor-Transistor Logic (TTL) and Complementary Metal-Oxide-Semiconductor (CMOS) logic families.

Fundamental Logic Gates

Combinational logic circuits respond instantaneously to input changes without storing historical state information. The primary logic gate functions are:

1. NOT Gate (Inverter)

The NOT gate performs boolean negation. It accepts a single input and outputs its inverse ($Y = \bar{A}$). If input $A = 0$, output $Y = 1$; if input $A = 1$, output $Y = 0$.

2. AND Gate

The AND gate produces a High (1) output if and only if all inputs are High ($Y = A \cdot B$). If any input is Low (0), the output remains Low. In avionics, AND gates are frequently used in safety interlock circuits, such as requiring both "Throttle at Idle" AND "Wheels on Ground" to enable thrust reverser deployment.

3. OR Gate

The OR gate produces a High (1) output if one or more inputs are High ($Y = A + B$). The output is Low only when all inputs are Low. OR gates are implemented in master warning systems where multiple sensor inputs (e.g., "Low Oil Pressure" OR "High Engine Temperature") trigger an annunciator light.

4. NAND Gate (Not-AND)

The NAND gate produces a Low (0) output only when all inputs are High ($Y = \overline{A \cdot B}$). For all other input combinations, the output is High.

5. NOR Gate (Not-OR)

The NOR gate produces a High (1) output only when all inputs are Low ($Y = \overline{A + B}$). If any input goes High, the output becomes Low.

6. XOR Gate (Exclusive-OR)

The XOR gate produces a High (1) output when the inputs are different, and a Low (0) output when the inputs are identical ($Y = A \oplus B = A\bar{B} + \bar{A}B$). XOR gates serve as parity generators and binary adders in flight data bus transceivers.

7. XNOR Gate (Exclusive-NOR)

The XNOR gate produces a High (1) output when the inputs are identical, and a Low (0) output when the inputs differ ($Y = \overline{A \oplus B}$). XNOR gates act as digital magnitude comparators.

Universal Logic Gates & De Morgan's Theorems

NAND and NOR gates are classified as universal logic gates because any fundamental boolean logic operation (NOT, AND, OR) can be constructed exclusively using only NAND gates or only NOR gates. Universal gate implementation simplifies semiconductor manufacturing and allows avionics technicians to substitute spare gate channels on multi-gate Integrated Circuit (IC) packages during emergency repair operations.

De Morgan's Theorems

De Morgan's laws provide mathematical equivalence equations used to simplify complex logic circuits and convert between gate types:

1. De Morgan's First Law: The complement of a product equals the sum of the complements: $\overline{A \cdot B} = \bar{A} + \bar{B}$ Interpretation: A NAND gate is functionally equivalent to an OR gate with inverted inputs (Negative-OR gate).

2. De Morgan's Second Law: The complement of a sum equals the product of the complements: $\overline{A + B} = \bar{A} \cdot \bar{B}$ Interpretation: A NOR gate is functionally equivalent to an AND gate with inverted inputs (Negative-AND gate).

Logic Gate Truth Table Matrix

The following truth table summarizes output logic states across all primary two-input gates for every input combination:

Positive Logic vs. Negative Logic Conventions

Logic polarity defines how physical electrical voltage levels map to logical binary values:

• Positive Logic: High Voltage ($V_H$) represents Logic 1; Low Voltage ($V_L$) represents Logic 0.
• Negative Logic: Low Voltage ($V_L$) represents Logic 1; High Voltage ($V_H$) represents Logic 0.

In aircraft schematic diagrams, active-low signals are identified by an overbar above the signal name ($\overline{\text{RESET}}$), a prefix slash (/RESET), or a small inversion bubble on the IC pin. For example, an aircraft landing gear proximity switch might short a signal line to chassis ground ($0\text{V}$) when the gear is locked down. Under negative logic, this $0\text{V}$ state represents Logic 1 ("True"), asserting the active-low $\overline{\text{GEAR_DOWN}}$ signal.

Logic Families: TTL vs. CMOS Characteristics

The two dominant semiconductor logic families utilized in aircraft electronic systems are Transistor-Transistor Logic (TTL) and Complementary Metal-Oxide-Semiconductor (CMOS).

Transistor-Transistor Logic (TTL)

TTL circuits (7400 series ICs) utilize bipolar junction transistors (BJTs). Standard TTL operates from a strictly regulated $+5.0\text{V} \pm 0.25\text{V}$ power supply.

Key TTL Voltage Thresholds:

• $V_{IH(\min)} = 2.0\text{V}$: Minimum voltage recognized as a High input.
• $V_{IL(\max)} = 0.8\text{V}$: Maximum voltage recognized as a Low input.
• $V_{OH(\min)} = 2.4\text{V}$: Minimum voltage guaranteed at a High output.
• $V_{OL(\max)} = 0.4\text{V}$: Maximum voltage guaranteed at a Low output.

Noise Margin Calculation: Noise margin represents a circuit's immunity to stray voltage spikes and electromagnetic noise:

• High-level Noise Margin ($NM_H$): $NM_H = V_{OH(\min)} - V_{IH(\min)} = 2.4\text{V} - 2.0\text{V} = 0.4\text{V}$.
• Low-level Noise Margin ($NM_L$): $NM_L = V_{IL(\max)} - V_{OL(\max)} = 0.8\text{V} - 0.4\text{V} = 0.4\text{V}$.

Complementary Metal-Oxide-Semiconductor (CMOS)

CMOS circuits (4000 series and 74HC/HCT series ICs) employ complementary pairs of P-channel and N-channel MOSFETs. CMOS supports wide supply voltage ranges (typically $3.0\text{V}$ to $15\text{V}$, or standard $3.3\text{V}$ / $5.0\text{V}$ rail logic).

Key CMOS Characteristics (at $5.0\text{V}$ supply):

• Input Thresholds: $V_{IH(\min)} \approx 70% V_{DD} = 3.5\text{V}$; $V_{IL(\max)} \approx 30% V_{DD} = 1.5\text{V}$.
• Output Voltages: $V_{OH(\min)} \approx 4.9\text{V}$; $V_{OL(\max)} \approx 0.1\text{V}$.
• Noise Immunity: CMOS noise margins are approximately $1.5\text{V}$ ($30% V_{DD}$), providing vastly superior noise immunity compared to TTL in high-EMI aircraft environments.
• Power Consumption: CMOS exhibits near-zero static current draw. Power dissipation occurs almost entirely during state switching ($P = C \cdot V^2 \cdot f$).

Avionics Technical Traps & Exam Watch

• Direct TTL-to-CMOS Interfacing Trap: Connecting a standard TTL gate output directly to a 5V CMOS gate input can cause intermittent signal failure. Because a TTL High output is only guaranteed to reach $2.4\text{V}$, it falls below the $3.5\text{V}$ minimum input threshold ($V_{IH}$) required by a 5V CMOS gate. Technicians must install a pull-up resistor to $+5\text{V}$ or use a level-shifting buffer IC (such as the 74HCT series).
• Unconnected Input Handling Trap: Unconnected (floating) TTL inputs naturally drift up to a High logic level (Logic 1), though leaving them floating makes them vulnerable to noise pickup. Conversely, floating CMOS inputs float unpredictably between logic thresholds, causing MOSFET linear conduction, severe overheating, and uncontrolled output oscillation. Unused CMOS gate inputs must always be tied directly to $V_{DD}$ or Ground.