3.2 Bipolar Junction Transistors, FETs, and Operational Amplifiers

3.2 Bipolar Junction Transistors, FETs, and Operational Amplifiers

Key Focus: Active semiconductor devices and integrated circuits provide signal amplification, mixing, buffering, and filtering across amateur equipment. Mastering current-controlled BJTs, voltage-controlled FETs, monolithic planar fabrication, and operational amplifier feedback topologies is vital for the ACMA Advanced Examination.

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Bipolar Junction Transistors (BJTs) and Biasing Stability

A BJT has emitter ($E$), base ($B$) and collector ($C$) regions. In forward-active operation, the base-emitter junction is forward biased and the collector-base junction reverse biased. For silicon, the forward junction voltage is commonly about 0.7 V at an illustrative operating current:

• NPN: Base is positive relative to emitter; collector is normally above base. Conventional base/collector currents enter the device and emitter current leaves it. The emitter arrow points outward.
• PNP: Bias polarities and conventional-current directions reverse: base is below emitter and collector below base. Current enters the emitter and leaves the collector/base. The emitter arrow points inward.

Using current magnitudes, $I_E=I_B+I_C$, $\beta=I_C/I_B$ and $\alpha=\beta/(\beta+1)$. A small base-current change controls a larger collector-current change; the actual gain depends on device and operating conditions.

Fundamental BJT Configurations and Thermal Stabilization

• Common Emitter (CE): Input at base, output at collector. Provides high voltage and current gain with $180^\circ$ phase inversion. At RF, collector-base capacitance ($C_{cb}$) causes capacitive feedback (the Miller effect), limiting high-frequency bandwidth.
• Common Collector (CC / Emitter Follower): Input at base, output at emitter. Delivers near-unity voltage gain ($A_v \approx 1$), high input impedance, low output impedance, and zero phase shift, acting as an isolation buffer.
• Common Base (CB): Input at emitter, output at collector. Provides unity current gain ($\alpha$), high voltage gain, and low input impedance ($20\ \Omega - 50\ \Omega$). Grounding the base shields the input from the output, eliminating the Miller effect in VHF/UHF preamplifiers.
• Thermal Runaway Prevention: Base-emitter forward voltage possesses a negative temperature coefficient: $\Delta V_{BE} / \Delta T \approx -2.0\text{ mV}/^\circ\text{C}$. Rising temperatures decrease $V_{BE}$, exponentially increasing $I_B$ and $I_C$ and risking destructive thermal runaway. Bias stability is achieved via voltage divider bias with an emitter degeneration resistor ($R_E$). The divider holds $V_B$ constant; as temperature increases $I_E$, the larger drop across $R_E$ forces $V_{BE} = V_B - I_E R_E$ down, throttling base drive and stabilizing the $Q$-point. An AC bypass capacitor ($C_E$) across $R_E$ prevents AC gain reduction.

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Field Effect Transistors (FETs) and CMOS Architecture

Field Effect Transistors are voltage-controlled, unipolar devices: conduction occurs strictly via majority carriers flowing from Source ($S$) to Drain ($D$) through a channel modulated by the Gate ($G$).

• Junction FET (JFET): Employs a reverse-biased gate junction. For an N-channel JFET, normal gate bias has $V_{GS}\le0$; a P-channel device uses the opposite polarity. Above pinch-off ($|V_p|$), drain current saturates at $I_D = I_{DSS}(1 - V_{GS}/V_p)^2$.
• MOSFETs: An ultra-thin silicon dioxide ($\text{SiO}_2$) layer insulates the gate ($Z_{in} > 10^{14}\ \Omega$), requiring ESD precautions. In depletion-mode, a channel exists at $V_{GS} = 0\text{ V}$; An N-channel enhancement-mode device requires positive gate-to-source voltage above its threshold; a P-channel device requires the opposite polarity.
• Dual-Gate MOSFETs: Feature two gates in series; Gate 1 receives RF while Gate 2 receives AGC bias or LO injection. Gate 2 acts as an electrostatic shield ($C_{gd} < 0.02\text{ pF}$), allowing gain control without detuning tuned circuits.
• CMOS Technology: Pairs complementary P-channel and N-channel MOSFETs. With one transistor always off in any static state, CMOS draws near-zero static DC power, consuming energy only during switching transitions ($P = C V^2 f$).
• RF Power Devices: LDMOS devices operate at $50\text{ V}$ rails with high gain and extreme mismatch tolerance (SWR $> 65:1$) for HF/VHF power amplifiers. GaN HEMTs exploit a wide bandgap ($3.4\text{ eV}$) for high efficiency into microwave bands.

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FET Amplifier Configurations

“Common” identifies the terminal held at signal reference, which need not be DC ground. For ordinary voltage-amplifier arrangements:

These correspond to common-emitter, common-base and emitter-follower BJT arrangements. Bias networks, loading, feedback and frequency alter the actual impedances; gate capacitance matters at RF.

Simple Integrated Circuits (ICs)

Monolithic integrated circuits fabricate active transistors, diodes, and resistors on a single monocrystalline silicon die using planar photolithography, diffusion, and metallization.

• Key Advantages:
  1. Matched Thermal Characteristics: Nearby components on one die track temperature closely. Matched differential-pair transistors reduce input offset and its temperature drift; real ICs retain finite offset and drift.
  2. Miniaturization & Density: Concentrates complex circuits into compact packages with minimal weight.
  3. Reduced Parasitics: Microscopic interconnects minimize stray lead inductances and capacitances.
• Linear vs Digital ICs:
  • Linear / Analogue ICs: Process continuous signals with proportional fidelity (e.g., op-amps, voltage regulators, RF mixers).
  • Digital ICs: Switch between discrete binary states (0 and 1) between saturation and cutoff (e.g., CMOS logic, microcontrollers, DDS chips).

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Operational Amplifiers and the Golden Rules

An operational amplifier (op-amp) is a high-gain direct-coupled differential amplifier.

• Ideal Characteristics: Infinite open-loop voltage gain ($A_{OL} \to \infty$), infinite input impedance ($Z_{in} \to \infty$), zero output impedance ($Z_{out} \to 0$), infinite bandwidth, and zero input offset voltage/drift ($V_{os} \to 0$, $\Delta V_{os}/\Delta T \to 0$).
• The Two Golden Rules of Negative Feedback:
  1. Rule 1: Zero current flows into either input terminal ($I_+ = I_- = 0$).
  2. Rule 2: Negative feedback drives differential input voltage to zero ($V_+ = V_-$). Grounding the non-inverting input ($V_+ = 0\text{ V}$) forces the inverting terminal to become a virtual ground ($V_- = 0\text{ V}$).

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Standard Op-Amp Topologies and Dynamic Limitations

• Inverting Amplifier: Input connects through $R_{in}$ to the inverting input with feedback resistor $R_f$. With the inverting terminal at virtual ground:

$$V_{out} = -\left(\frac{R_f}{R_{in}}\right) V_{in} \quad \text{and} \quad Z_{in} = R_{in}$$

• Non-Inverting Amplifier: Signal enters the non-inverting terminal ($+$) directly; $R_1$ and $R_f$ form a feedback divider to ($-$). With $Z_{in} \to \infty$:

$$V_{out} = \left(1 + \frac{R_f}{R_1}\right) V_{in}$$

• Voltage Follower (Buffer): Direct output-to-inverting feedback ($R_f = 0$): $V_{out} = V_{in}$ ($A_v = 1$, high $Z_{in}$, low $Z_{out}$).
• Summing Amplifier: Multiple inputs sum into the inverting virtual ground node without crosstalk: $V_{out} = -(R_f/R_1 \cdot V_1 + R_f/R_2 \cdot V_2)$, used in audio mixers and CTCSS encoders.
• Difference Amplifier: Rejects common-mode hum and RF pickup across balanced lines: $V_{out} = (R_f/R_1)(V_2 - V_1)$, characterized by its Common-Mode Rejection Ratio (CMRR).
• Active Filters: A second-order Sallen-Key low-pass stage rolls off at $-12\text{ dB/octave}$. Op-amp band-pass filters select SSB speech ($300\text{ Hz} - 2.8\text{ kHz}$) or narrower CW audio bands without bulky inductors.
• Comparator and Schmitt Trigger: Open-loop operation compares inputs, saturating to supply rails ($\pm V_{sat}$). Adding positive feedback introduces hysteresis ($V_H = \text{UTP} - \text{LTP}$), eliminating chatter when squaring noisy signals.
• Dynamic Limits:
  • Gain-Bandwidth Product (GBWP): For a dominant-pole voltage-feedback op-amp, $f_c \approx \text{GBWP}/G_N$, where $G_N$ is noise gain. An inverting stage has $G_N=1+R_f/R_{in}$; a non-inverting stage has noise gain equal to its signal gain.
  • Slew Rate (SR): Maximum rate of output change ($\text{V}/\mu\text{s}$), restricting full-power bandwidth to $f_{\text{max}} = \text{SR} / (2 \pi V_p)$.

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Circuit Topologies Comparison

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Worked Engineering Calculations

Example 1: Op-Amp Audio Stage Gain and Bandwidth

Problem: An inverting op-amp stage has $R_{in} = 10\text{ k}\Omega$ and $R_f = 100\text{ k}\Omega$, using an op-amp with $\text{GBWP} = 3.0\text{ MHz}$ and $\text{SR} = 1.5\text{ V}/\mu\text{s}$. Calculate the closed-loop gain ($A_v$), input impedance ($Z_{in}$), $-3\text{ dB}$ bandwidth ($f_c$), and maximum peak voltage ($V_p$) at $f = 2.5\text{ kHz}$ without slew distortion.

Solution:

1. Gain and Input Impedance:

$$A_v = -\frac{R_f}{R_{in}} = -\frac{100\text{ k}\Omega}{10\text{ k}\Omega} = -10 \quad (|A_v| = 10) \quad \text{and} \quad Z_{in} = R_{in} = 10\text{ k}\Omega$$

1. Closed-Loop Bandwidth and Slew Limit:

$$G_N=1+\frac{100}{10}=11, \qquad f_c \approx \frac{\text{GBWP}}{G_N}=\frac{3,000,000\text{ Hz}}{11}\approx273\text{ kHz}$$ $$V_p = \frac{\text{SR}}{2 \pi f} = \frac{1.5 \times 10^6\text{ V/s}}{2 \times \pi \times 2,500\text{ Hz}} \approx 95.5\text{ V}$$

(Output swing is limited by the power rails rather than slew rate).

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Example 2: BJT Voltage Divider Bias Operating Point ($Q$-Point)

Problem: An NPN BJT ($\beta = 100$, $V_{BE} = 0.7\text{ V}$) is biased with $V_{CC} = 12\text{ V}$, $R_1 = 33\text{ k}\Omega$, $R_2 = 10\text{ k}\Omega$, $R_C = 2.2\text{ k}\Omega$, and $R_E = 680\ \Omega$. Calculate $V_B$, $I_C$, and $V_{CE}$.

Solution:

1. Include Divider Loading: Replace the bias divider by its Thevenin equivalent:

$$V_{TH}=12\frac{10}{33+10}=2.791\text{ V}, \qquad R_{TH}=\frac{33\times10}{33+10}=7.674\text{ k}\Omega$$

The base current causes a voltage drop across $R_{TH}$. With $I_E=(\beta+1)I_B$:

$$I_B=\frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E}=\frac{2.791-0.700}{7674+101\times680}\approx27.38\ \mu\text{A}$$ $$I_C=\beta I_B\approx2.738\text{ mA}, \quad V_E=(\beta+1)I_BR_E\approx1.881\text{ V}, \quad V_B=V_E+0.700\approx2.581\text{ V}$$

1. Collector-Emitter Voltage:

$$V_C=12-(2.738\text{ mA})(2.2\text{ k}\Omega)\approx5.976\text{ V}$$ $$V_{CE}=V_C-V_E\approx5.976-1.881=4.096\text{ V}$$

The collector is above the base, consistent with forward-active NPN operation. Ignoring base current would be an approximation; here it substantially changes the calculated operating point.