4.2 Phase-Locked Loops (PLLs) and Frequency Synthesisers

4.2 Phase-Locked Loops (PLLs) and Frequency Synthesisers

While a quartz crystal oscillator provides exceptional frequency stability and low phase noise, it operates at only one fixed frequency (or across a tiny "rubbering" range of a few kilohertz). Modern amateur transceivers, however, must tune continuously across dozens of megahertz with sub-hertz channel resolution while retaining the absolute accuracy and stability of an atomic or crystal reference. This capability is realized through frequency synthesis, primarily using the Phase-Locked Loop (PLL).

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PLL Fundamentals and Closed-Loop Control Theory

A Phase-Locked Loop is a closed-loop negative feedback system. In a synthesiser, it adjusts the VCO until the divided VCO signal matches the comparison reference in frequency and has a stable phase relationship to it.

f_osc ->[/R]-> f_ref ->[PFD]->[CP]->[LF]->[VCO]---+--> f_out
                         ^                        |
                         |                        |
                         +--- f_div <-[/N]<-------+

LF is the loop filter. For a $10\text{ MHz}$ master reference, $R=800$ gives $f_{\text{ref}}=12.5\text{ kHz}$. With $N=11600$, the locked output is $145\text{ MHz}$.

Mathematical Formulation of the Closed Loop

Near lock, use an averaged small-signal phase model in the Laplace domain. The comparison-reference phase is $\Phi_{\text{ref}}(s)$, and the divided feedback phase is $\Phi_{\text{out}}(s)/N$.

1. Phase Detector Transfer Gain ($K_d$): Converts phase error $\Theta_e(s) = \Phi_{\text{ref}}(s) - \Phi_{\text{div}}(s)$ into current pulses (for a charge pump) or voltage:

$$I_{\text{cp}}(s) = K_d \times \Theta_e(s) = \left( \frac{I_{\text{CP}}}{2\pi} \right) \Theta_e(s) \quad [\text{A/rad}]$$

1. Loop Filter Transfer Impedance ($Z_{\text{LF}}(s)$): Converts the charge pump current into control voltage $V_{\text{tune}}(s)$:

$$V_{\text{tune}}(s) = I_{\text{cp}}(s) \times Z_{\text{LF}}(s)$$

1. VCO Transfer Function ($K_{\text{vco}}$): An oscillator is an ideal integrator of frequency to phase ($\phi(t) = \int \omega(t) dt$). In the Laplace domain, integration is represented by $1/s$:

$$\Phi_{\text{out}}(s)=\frac{K_{\text{vco}}}{s}V_{\text{tune}}(s),\qquad [K_{\text{vco}}]=\text{rad}/(\text{s}\cdot\text{V})$$

1. Feedback Divider ($1/N$): Scales down the output phase:

$$\Phi_{\text{div}}(s) = \frac{\Phi_{\text{out}}(s)}{N}$$

Define the loop gain, including the divider, as:

$$G(s)=\frac{K_dK_{\text{vco}}Z_{\text{LF}}(s)}{sN},\qquad H(s)=\frac{\Phi_{\text{out}}}{\Phi_{\text{ref}}}=\frac{NG(s)}{1+G(s)}$$

Neglecting the small high-frequency capacitor $C_2$, the filter has $Z_{\text{LF}}=R_1+1/(sC_1)$. With $K=K_dK_{\text{vco}}/N$, this gives:

$$H(s)=N\frac{2\zeta\omega_ns+\omega_n^2}{s^2+2\zeta\omega_ns+\omega_n^2},\quad\omega_n^2=\frac{K}{C_1},\quad2\zeta\omega_n=KR_1$$

Here $\omega_n$ is natural angular frequency, not generally the loop's cutoff frequency. The damping ratio $\zeta\approx0.707$ is a common underdamped design choice; $\zeta=1$ is critical damping. Including $C_2$ adds another pole and requires a higher-order stability check.

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Core Functional Blocks of the Synthesiser

1. Reference Oscillator and Reference Divider ($\div R$)

The reference oscillator provides the timing foundation for the entire synthesiser. In commercial and amateur equipment, this is a TCXO (Temperature Compensated Crystal Oscillator) with stability of $\pm 0.5\text{ to }\pm 2.5\text{ ppm}$, or an OCXO (Oven Controlled Crystal Oscillator) offering stabilities down to $\pm 0.01\text{ ppm}$.

A programmable digital reference divider ($\div R$) divides the master reference frequency ($f_{\text{osc}}$, typically $10.0\text{ MHz}$ or $19.2\text{ MHz}$) down to the comparison reference frequency ($f_{\text{ref}}$):

$$f_{\text{ref}} = \frac{f_{\text{osc}}}{R}$$

2. Phase-Frequency Detector (PFD) and Charge Pump

Early PLLs utilized simple analog multipliers (double-balanced Gilbert cell mixers) or digital XOR gates as phase detectors. However, these circuits suffered from narrow pull-in ranges (lock ranges of only a few kilohertz) and could falsely lock onto odd harmonics of the reference.

Modern synthesisers universally employ the digital tri-state Phase-Frequency Detector (PFD), constructed from two D-type flip-flops and an internal reset AND gate:

f_ref --> [DFF1: D=1] --> UP   --> Charge-pump source
f_div --> [DFF2: D=1] --> DOWN --> Charge-pump sink

UP, DOWN --> [AND] --> [Reset delay] --> CLR1 and CLR2

Each DFF is clocked by its labelled input edge.
The delayed AND output clears both DFFs.

• Tri-State Operational Modes:

  1. State 1 (VCO lagging or lower frequency): The rising edge of $f_{\text{ref}}$ arrives before the edge of $f_{\text{div}}$. The top flip-flop triggers, asserting the UP pulse high. The charge pump switches on its constant-current source ($+I_{\text{CP}}$), pumping charge into the loop filter to raise $V_{\text{tune}}$ and increase VCO frequency.
  2. State 2 (VCO leading or higher frequency): The rising edge of $f_{\text{div}}$ arrives first. The bottom flip-flop triggers, asserting the DOWN pulse high. The charge pump turns on its constant-current sink ($-I_{\text{CP}}$), draining charge from the loop filter to lower $V_{\text{tune}}$ and decrease VCO frequency.
  3. State 3 (Locked state): Nearly coincident edges produce short UP and DOWN pulses before reset. In the ideal matched pump their average currents balance. The filter holds the required tuning voltage between updates; real mismatch and leakage can produce ripple and a small phase offset.

• Frequency-Sensitive Acquisition: The PFD indicates which input is faster as well as which edge leads. This guides acquisition from larger frequency errors than a phase-only detector and avoids its harmonic-lock ambiguity. Successful lock still requires the target to lie within the VCO/control range and the detector's operating limits.

• The Dead-Zone Phenomenon: Very short pulses may fail to switch the charge pump reliably. An intentional reset delay produces anti-backlash pulses even near zero phase error, reducing this dead zone. Pump mismatch and switching transients still matter for phase noise and reference spurs.

3. The Loop Filter (Low-Pass Filter)

The loop filter is the electrical heart of the PLL. It performs three critical tasks:

1. It integrates the discrete current pulses ($+I_{\text{CP}} / -I_{\text{CP}}$) from the charge pump into a smooth, continuous analog DC tuning voltage ($V_{\text{tune}}$).
2. It attenuates high-frequency reference ripple and charge pump switching transients before they can modulate the VCO.
3. It establishes the dynamic control loop parameters: natural frequency ($\omega_n$), damping factor ($\zeta$), and phase margin.

A typical second-order passive lead-lag loop filter consists of a series resistor $R_1$ and capacitor $C_1$, shunted by a smaller capacitor $C_2$:

  From Charge                                           To VCO
  Pump Output                                         Tuning Input
       o------------------------+--------------------------o
                                |                          |
                               --- C_2                    [R_1]
                               ---                        |
                                |                         --- C_1
                                |                         ---
                                |                          |
                               ///                        ///

• $C_1$ acts as the primary integrator, accumulating charge to set the steady-state DC voltage.
• $R_1$ introduces a zero that supplies phase lead and improves phase margin. Without it, the loop-filter capacitor and the VCO provide two ideal integrators, giving an undamped loop model. Actual stability also depends on the additional poles and delays.
• $C_2$ (typically sized at $C_2 \approx C_1 / 10$) adds a high-frequency pole to smooth the sharp voltage steps across $R_1$ caused by the charge pump current edges, attenuating reference ripple.

4. The Voltage-Controlled Oscillator (VCO)

The VCO is an LC oscillator whose resonant frequency is electronically tuned by varactor (varicap) diodes. When reverse-bias tuning voltage $V_{\text{tune}}$ increases, the varactor depletion layer widens, reducing its junction capacitance ($C_v$) and increasing the oscillator frequency:

$$f_{\text{out}} = \frac{1}{2\pi \sqrt{L (C_{\text{fixed}} + C_v(V_{\text{tune}}))}}$$

The sensitivity of the VCO is denoted by its tuning gain $K_{\text{vco}}$, defined in megahertz per volt ($\text{MHz/V}$) or radians per second per volt:

$$K_{\text{vco}} = 2\pi \times \frac{\Delta f}{\Delta V_{\text{tune}}} \quad [\text{rad}/(\text{s}\cdot\text{V})]$$

Because varactor capacitance is non-linear ($C_v \propto (V_{\text{tune}})^{-n}$), $K_{\text{vco}}$ varies across the tuning band, requiring careful loop filter design to maintain stability across all operating frequencies.

5. Programmable Frequency Divider ($\div N$)

The programmable frequency divider is a digital counter that decrements from a loaded binary integer $N$ down to zero, outputting one pulse for every $N$ input cycles from the VCO:

$$f_{\text{div}} = \frac{f_{\text{out}}}{N}$$

When the loop achieves phase lock, the PFD forces $f_{\text{div}} = f_{\text{ref}}$. Consequently, the synthesised output frequency is an exact integer multiple of the reference comparison frequency:

$$f_{\text{out}} = N \times f_{\text{ref}} = N \times \left( \frac{f_{\text{osc}}}{R} \right)$$

Changing the integer $N$ in the divider's control register steps the output frequency in discrete increments equal to $f_{\text{ref}}$:

$$\Delta f_{\text{channel}} = f_{\text{ref}}$$

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Performance Trade-Offs in PLL Synthesiser Design

Designing a high-performance amateur radio PLL synthesiser involves balancing conflicting engineering trade-offs between lock time, phase noise, channel step size, and reference spurs.

The Loop Bandwidth Compromise

The loop bandwidth $B_L$ describes the range of offset frequencies over which feedback substantially corrects the VCO. Its relation to natural frequency $\omega_n$ depends on damping and loop order; it separates two approximate regimes:

1. Inside the Loop Bandwidth: Feedback suppresses VCO noise at sufficiently low offsets. The reference phase-noise component at the PFD input is transferred to the output with approximately $20\log_{10}N$ amplification. PFD, charge-pump and divider noise also contribute, so this component alone is not the total output noise:

$$\mathcal{L}_{\text{out,ref}}(f)\approx\mathcal{L}_{\text{ref at PFD}}(f)+20\log_{10}N\quad[\text{dBc/Hz}]$$

For a fixed reference-noise component, doubling $N$ raises that component by $6.02\text{ dB}$. If the same master oscillator is first divided by $R$, its net low-offset phase multiplication is $N/R$, not $N$.

1. Outside the Loop Bandwidth: Feedback provides progressively less correction. The free-running VCO noise usually dominates, although other circuit noise can still contribute. The transition is gradual rather than a sharp boundary.

Reference Spurs

Even in a locked condition, tiny leakage currents through the charge pump switches and parasitic capacitance discharge periodically pulse the loop filter at the comparison frequency $f_{\text{ref}}$. This periodic ripple modulates $V_{\text{tune}}$, frequency-modulating the VCO and producing discrete sideband spikes known as reference spurs at frequency offsets of:

$$f_{\text{spur}} = f_{\text{out}} \pm k f_{\text{ref}} \quad (k \in \{1, 2, 3, \dots\})$$

In a receiver, reference spurs can mix with strong adjacent-channel signals, converting them directly into the intermediate frequency (reciprocal mixing) and masking weak desired signals. Suppressing reference spurs requires ultra-low-leakage charge pump design and adding extra low-pass filtering poles (e.g. $C_2, C_3$) in the loop filter.

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High-Frequency Division: Dual-Modulus Prescalers and Pulse-Swallow Counters

At VHF and UHF, a high-speed prescaler reduces the RF clock rate before the larger programmable counters. This lets the counters use slower, lower-power circuitry; the attainable RF frequency depends on the chosen IC, rather than on a universal CMOS speed limit.

To overcome this, engineers utilize a dual-modulus prescaler coupled to a pulse-swallow counter:

RF -> [Prescaler P/(P+1)]---+--> [M counter] --> f_div to PFD
            ^               |
            |               +--> [S counter] ---+
            |                                   |
            +---- modulus control <-------------+

M timeout reloads both M and S and restores P+1 mode.

• Dual-Modulus Prescaler ($P / P+1$): A high-speed divider capable of dividing by either $P$ or $P+1$ based on a logic state on its modulus control line (typical prescaler values are $32/33$ or $64/65$).
• Main Counter ($M$) and Swallow Counter ($S$): Both are clocked by the prescaler output and reloaded together. For the simple cycle shown, choose $0\le S<P$ and $S\le M$, within the IC's permitted counter values.

Pulse-Swallowing Operating Cycle

1. At cycle start, the prescaler is set to divide by $P + 1$. Both $M$ and $S$ count down from their preset values.
2. After $S$ output pulses from the prescaler, the Swallow Counter reaches zero, halts, and flips the modulus control line to force the prescaler to divide by $P$.
3. The total RF cycles elapsed during this first phase is:
   $N_1 = S \times (P + 1)$
4. The Main Counter continues counting down for the remaining $(M - S)$ pulses at the divide-by-$P$ rate before it reaches zero.
5. The total RF cycles elapsed during this second phase is:
   $N_2 = (M - S) \times P$
6. When the Main Counter reaches zero, it outputs a single pulse to the PFD, reloads both $M$ and $S$ counters, and the cycle repeats.

Summing the RF cycles over the complete sequence reveals the total effective division ratio $N$:

$$N = N_1 + N_2 = S(P + 1) + (M - S)P = SP + S + MP - SP = M \cdot P + S$$

Varying $S$ provides unit steps in $N=MP+S$ within the legal divide range. For this ideal dual-modulus arrangement, all consecutive $N\ge P(P-1)$ are representable; a particular IC may impose further counter or operating limits.

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Integer-$N$ vs. Fractional-$N$ Frequency Synthesisers

The Fundamental Limitation of Integer-$N$ Synthesisers

In an Integer-$N$ PLL, the output channel step size is strictly equal to the reference comparison frequency ($\Delta f = f_{\text{ref}}$). For narrow-band amateur modes (CW, SSB), channel steps of $10\text{ Hz}$ or $100\text{ Hz}$ are required. Setting $f_{\text{ref}} = 100\text{ Hz}$ creates severe performance bottlenecks:

• To generate a $144\text{ MHz}$ signal with $f_{\text{ref}} = 100\text{ Hz}$, the division ratio must be $N = 144,000,000 / 100 = 1,440,000$.
• The reference component at the PFD input is multiplied by $20\log_{10}(1,440,000)\approx123.2\text{ dB}$. This is a transfer term, not a complete prediction of the synthesiser's phase noise.
• The low comparison frequency restricts useful loop bandwidth. A bandwidth well below the comparison frequency helps limit sampling effects and ripple; settling depends on damping, frequency step and the permitted final error.

The Fractional-$N$ Synthesiser Architecture

A Fractional-$N$ Synthesiser breaks the rigid lock between channel step size and reference frequency. It allows the effective division ratio to take non-integer, fractional values:

$$N_{\text{eff}} = N + \frac{K}{F}$$

where $N$ is the integer portion, $K$ is the fractional numerator, and $F$ is the fractional modulus (accumulator capacity).

                               Average Division Ratio:
                              N_eff = N + (K / F)
                           +------------------------+
  f_out ------------------>|  Dual-Modulus Divider  |-----> f_div to PFD
                           |      ÷N  or  ÷(N+1)    |
                           +------------------------+
                                       ^
                                       | Carry Out (Selects ÷(N+1))
                           +------------------------+
  f_ref ------------------>|  Digital Accumulator   |
                           |     (Capacity F)       |
                           +------------------------+
                                       ^
                                       | Frequency Word (K)

• Principle of Operation: The divider alternates dynamically between dividing by $N$ and $N + 1$. For example, to divide by $10.25$, the divider divides by $10$ for three reference cycles and by $11$ for one cycle, producing an average division ratio of:

$$N_{\text{eff}} = \frac{10 + 10 + 10 + 11}{4} = \frac{41}{4} = 10.25$$

• Fine Frequency Grid: The step size is $\Delta f=f_{\text{ref}}/F$. A large modulus permits fine steps while keeping the comparison frequency high and $N$ relatively low. This can improve the noise/settling trade-off, but actual performance depends on the PLL, VCO, loop filter and fractional spurs.
• Fractional Spurs and Sigma-Delta ($\Sigma\Delta$) Modulation: Repeating divider sequences create periodic phase errors and spurious tones; their offsets depend on the sequence. Sigma-delta divider control preserves the required average ratio while shaping quantization noise toward higher offsets, where the loop filter provides more attenuation. It does not eliminate all fractional or integer-boundary spurs. Modulator settings, frequency planning and loop bandwidth must control both tones and shaped noise.

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Comparison of Synthesiser Architectures

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Worked Engineering Calculations

Example 1: Integer-$N$ Synthesiser Design for a 2-Meter VHF Transceiver

Problem: An amateur $2\text{-meter}$ VHF FM transceiver covers $144.000\text{ MHz}$ to $148.000\text{ MHz}$ with a standard channel spacing of $12.5\text{ kHz}$. A master $10.000\text{ MHz}$ TCXO reference is used. Calculate:

1. The required reference divider ratio ($R$).
2. The minimum and maximum programmable divider ratios ($N_{\text{min}}$ and $N_{\text{max}}$).
3. The theoretical phase noise penalty introduced by the divider ratio at $144.000\text{ MHz}$.

Solution:

1. Reference Divider Ratio ($R$): The reference comparison frequency must match channel spacing ($f_{\text{ref}} = 12.5\text{ kHz}$):

$$R = \frac{f_{\text{osc}}}{f_{\text{ref}}} = \frac{10.000\text{ MHz}}{12.5\text{ kHz}} = \frac{10,000,000\text{ Hz}}{12,500\text{ Hz}} = 800$$

1. Divider Integer Values:

$$N_{\text{min}} = \frac{f_{\text{out(min)}}}{f_{\text{ref}}} = \frac{144.000\text{ MHz}}{12.5\text{ kHz}} = \frac{144,000\text{ kHz}}{12.5\text{ kHz}} = 11,520$$ $$N_{\text{max}} = \frac{f_{\text{out(max)}}}{f_{\text{ref}}} = \frac{148.000\text{ MHz}}{12.5\text{ kHz}} = \frac{148,000\text{ kHz}}{12.5\text{ kHz}} = 11,840$$

1. Phase Noise Penalty:

$$\Delta \mathcal{L} = 20 \log_{10}(N_{\text{min}}) = 20 \log_{10}(11,520) \approx 20 \times 4.06145 \approx 81.23\text{ dB}$$

The reference component measured at the PFD input is multiplied by $81.23\text{ dB}$ inside the loop bandwidth. Relative to the original $10\text{ MHz}$ TCXO, the ideal net multiplication is $N/R=14.4$, or $23.17\text{ dB}$. Additional circuit noise must be included separately.

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Example 2: Pulse-Swallow Prescaler Values

Problem: A UHF synthesiser uses a $32/33$ dual-modulus prescaler ($P = 32$) to synthesize $f_{\text{out}} = 432.500\text{ MHz}$ with a comparison frequency $f_{\text{ref}} = 25\text{ kHz}$. Determine the required Main Counter value ($M$) and Swallow Counter value ($S$).

Solution:

1. Total Division Ratio ($N$):

$$N = \frac{f_{\text{out}}}{f_{\text{ref}}} = \frac{432,500\text{ kHz}}{25\text{ kHz}} = 17,300$$

1. Calculating $M$ and $S$ using $N = M \cdot P + S$:

$$M = \left\lfloor \frac{N}{P} \right\rfloor = \left\lfloor \frac{17,300}{32} \right\rfloor = \lfloor 540.625 \rfloor = 540$$ $$S = N - (M \times P) = 17,300 - (540 \times 32) = 17,300 - 17,280 = 20$$

1. Verify Constraints:

• $S = 20 < P = 32$ (Valid: swallow counter does not exceed prescaler modulus).
• $S = 20 < M = 540$ (Valid: swallow counter terminates before main counter finishes).
  Result: $M = 540$, $S = 20$.

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Example 3: Fractional Grid and Phase-Noise Transfer

Problem: Compare a $432\text{ MHz}$ target using (A) integer-$N$ with $f_{\text{ref}}=100\text{ Hz}$ and (B) fractional-$N$ with $f_{\text{ref}}=25\text{ MHz}$ and $F=2^{18}=262144$. Both derive their reference from the same $25\text{ MHz}$ master. Assess divider ratios, frequency resolution and reference-noise transfer.

1. Integer-$N$:

$$R_A=250000,\qquad N_A=\frac{432000000}{100}=4320000,\qquad20\log_{10}N_A=132.71\text{ dB}$$

2. Fractional-$N$ frequency grid: The desired average ratio is $432/25=17.28$. Its fractional numerator would be $0.28F=73400.32$, which is not an integer. Choose the nearest $K=73400$:

$$f_B=\left(17+\frac{73400}{262144}\right)25000000\approx431999969.48\text{ Hz}$$

This is about $30.52\text{ Hz}$ below the target. The available step is:

$$\Delta f=\frac{25000000}{262144}\approx95.37\text{ Hz}$$

Thus the resolution is finer than $100\text{ Hz}$, but neither the exact target nor every $100\text{ Hz}$ channel lies on this grid.

3. Reference-noise transfer: The fractional divider term is approximately $20\log_{10}(17.28)=24.75\text{ dB}$. Subtracting it from $132.71\text{ dB}$ gives $107.96\text{ dB}$, but this is not the output-noise improvement. The integer system's reference divider already reduces the master's phase fluctuations. For both systems, the ideal low-offset master-to-output ratio is approximately:

$$\frac{N}{R}=\frac{432\text{ MHz}}{25\text{ MHz}}=17.28$$

The master's reference-noise contribution therefore has essentially the same $24.75\text{ dB}$ multiplication. A fair total-noise comparison also needs the PFD/charge-pump, divider, quantization and VCO noise with their loop responses.