11.1 Computer Fundamentals & Hardware Architecture

Computer Fundamentals & Hardware Architecture

In modern electronic banking systems, core banking platforms, automated teller machines (ATMs), and payment gateways rely on high-performance computing hardware. A thorough understanding of computer organization, central processing unit (CPU) architecture, memory hierarchy, and digital data representation is essential for solving high-level Computer Aptitude problems in the SBI PO Main examination.

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1. Computer Organization & Architecture Models

Computer architecture defines the conceptual design and fundamental operational structure of a computer system. The two primary architectural models encountered in system design are the Von Neumann Architecture and the Harvard Architecture.

Von Neumann vs. Harvard Architecture

+-----------------------------------------------------------------------+
|                      VON NEUMANN ARCHITECTURE                         |
|                                                                       |
|   +-------------------+    Control Bus    +-----------------------+   |
|   |    Central        |<=================>|      Main Memory      |   |
|   |  Processing Unit  |                   | (RAM - Stores Code    |   |
|   |     (CPU)         |==== Address Bus =>|     and Data Jointly) |   |
|   |  [ALU, CU, Regs]  |<== Data Bus =====>|                       |   |
|   +-------------------+                   +-----------------------+   |
+-----------------------------------------------------------------------+

The Von Neumann Bottleneck

In Von Neumann systems, because the CPU and memory share a single data bus, the CPU cannot read an instruction and read/write user data at the exact same instant. This throughput limitation is called the Von Neumann Bottleneck. System designers mitigate this bottleneck by implementing high-speed CPU Cache Memory between the processor and main memory.

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2. CPU Internal Components & Instruction Cycle

The Central Processing Unit (CPU) acts as the computational engine of the computer. It executes instructions stored in main memory through three primary sub-components:

1. Control Unit (CU): Directs the operation of the processor. It fetches instructions from main memory, decodes them, and coordinates data flow between the ALU, registers, and external peripherals by generating timing and control signals.
2. Arithmetic Logic Unit (ALU): Performs basic arithmetic calculations (addition, subtraction, multiplication) and logical operations (AND, OR, NOT, bitwise shifts, comparison of numerical values).
3. Processor Registers: Ultra-fast, internal high-speed storage locations situated directly inside the CPU package.

Key CPU Registers & Functions

• Program Counter (PC): Holds the memory address of the next instruction to be fetched and executed. It increments automatically after an instruction fetch.
• Instruction Register (IR): Holds the instruction currently being decoded and executed.
• Memory Address Register (MAR): Holds the physical RAM memory address currently being accessed for a read or write operation.
• Memory Data Register (MDR) / Memory Buffer Register (MBR): Holds the actual data payload read from memory or waiting to be written into memory.
• Accumulator (ACC): Holds intermediate arithmetic and logic results generated by the ALU.
• Stack Pointer (SP): Stores the address of the top of the stack frame in memory.

The Fetch-Decode-Execute Cycle

Every machine instruction is processed in a continuous sequence known as the Instruction Cycle:

$\text{Fetch} \longrightarrow \text{Decode} \longrightarrow \text{Execute} \longrightarrow \text{Store Result}$

1. Fetch: The Control Unit reads the instruction residing at the memory address specified by the Program Counter (PC) and loads it into the Instruction Register (IR). The PC is then incremented.
2. Decode: The Control Unit decodes the binary opcode in the IR to determine the operation and identify any required operands.
3. Execute: The ALU executes the operation on the specified operands (e.g., adding two numbers stored in registers).
4. Store Result: The final output is written back to the Accumulator register or main memory.

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3. Memory Hierarchy & Characteristics

Computer memory is arranged in a multi-level hierarchy balancing speed, capacity, and cost per bit. Speed decreases while storage capacity increases as you move down the hierarchy.

RAM Technologies: SRAM vs. DRAM

• Static RAM (SRAM): Uses 6-transistor (6T) flip-flop circuits per bit. Does not require periodic electrical refreshing. It is extremely fast, highly expensive, and power-hungry; used exclusively for CPU cache.
• Dynamic RAM (DRAM): Uses a single transistor and capacitor per bit. Capacitors leak electrical charge and must be refreshed thousands of times per second (refresh cycles). It offers high density and low cost; used for primary system RAM.

ROM Types (Non-Volatile System Firmware)

• ROM (Read-Only Memory): Factory programmed; cannot be altered.
• PROM (Programmable ROM): Blank chip that can be written to once using a specialized high-voltage programmer.
• EPROM (Erasable PROM): Data erased by exposing the chip to intense Ultraviolet (UV) light through a quartz window.
• EEPROM (Electrically Erasable PROM): Data erased electrically in blocks; forms the technical foundation for modern Flash memory and system BIOS/UEFI.

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4. Number Systems & Data Representation

Digital computers process data using binary logic levels ($0$ and $1$). Banking aptitude tests frequently evaluate numerical conversions between Binary (Base 2), Octal (Base 8), Decimal (Base 10), and Hexadecimal (Base 16).

Number Base Summary

• Binary (Base 2): Digits {0, 1}
• Octal (Base 8): Digits {0, 1, 2, 3, 4, 5, 6, 7}
• Decimal (Base 10): Digits {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}
• Hexadecimal (Base 16): Digits {0-9, A=10, B=11, C=12, D=13, E=14, F=15}

Step-by-Step Worked Conversion Example

Problem: Convert the Decimal integer $156_{10}$ into its Binary and Hexadecimal equivalents, and find its 8-bit 2's Complement representation for $-156_{10}$ (or $-28_{10}$ for 8-bit signed range).

Step A: Convert $156_{10}$ to Binary

Divide $156$ successively by $2$ and record the remainders from bottom to top:

• $156 \div 2 = 78$ remainder 0
• $78 \div 2 = 39$ remainder 0
• $39 \div 2 = 19$ remainder 1
• $19 \div 2 = 9$ remainder 1
• $9 \div 2 = 4$ remainder 1
• $4 \div 2 = 2$ remainder 0
• $2 \div 2 = 1$ remainder 0
• $1 \div 2 = 0$ remainder 1

Reading remainders bottom to top gives: $10011100_2$.

Step B: Convert Binary $10011100_2$ to Hexadecimal

Group the binary bits into 4-bit nibbles from right to left:

• Left Nibble: $1001_2 = 8 + 0 + 0 + 1 = 9_{16}$
• Right Nibble: $1100_2 = 8 + 4 + 0 + 0 = 12_{10} = \text{C}_{16}$
• Hexadecimal result: $9\text{C}_{16}$.

Step C: 2's Complement Representation of $-28_{10}$ (8-bit)

To represent negative signed integers in hardware:

1. Positive $+28_{10}$ in 8-bit binary: $00011100_2$
2. Take 1's Complement (invert all bits): $11100011_2$
3. Add $1$ to get 2's Complement: $11100011 + 1 = 11100100_2$

• Therefore, $-28_{10} = 11100100_2$.

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5. System Bus Architecture & Memory Addressing

A Bus is a shared collection of parallel electrical conductor lines transferring signals between computer hardware components.

+-----------------------------------------------------------------+
|                     SYSTEM BUS ARCHITECTURE                     |
|                                                                 |
|               +-------------------------------+                 |
|               |     Control Bus (Control/Status)  |             |
|               +-------------------------------+                 |
|       +-------------------------------------------------+       |
|       |  CPU  |<===>| Address Bus (Unidirectional) |===>| RAM/  |
|       |       |<===>| Data Bus (Bidirectional)     |<==>| Periph|
|       +-------------------------------------------------+       |
+-----------------------------------------------------------------+

Bus Types

• Address Bus: Unidirectional bus carrying physical memory addresses generated by the CPU to RAM and I/O devices. The width of the address bus determines the maximum addressable memory capacity.
• Data Bus: Bidirectional bus transferring actual data bytes between CPU registers, memory, and peripheral controllers.
• Control Bus: Transfers command signals (Read/Write, Interrupt Request, Bus Ack, Clock Signals) from the Control Unit.

Memory Addressability Formula

If an address bus has $N$ parallel lines, it can directly address $2^N$ unique byte locations:

$\text{Addressable RAM Capacity} = 2^N \text{ bytes}$

Calculation Example: A system with a 32-bit address bus can address: $2^{32} \text{ bytes} = 4,294,967,296 \text{ bytes} = 4 \text{ Gigabytes (GB)}$ A 64-bit address bus can theoretically address $2^{64} \text{ bytes} = 16 \text{ Exabytes (EB)}$.

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Exam Strategies & Common Traps

1. Address Bus vs. Data Bus Directionality: Remember that the Address Bus is strictly unidirectional (CPU to Memory/Peripherals), whereas the Data Bus is bidirectional.
2. Bit vs. Byte Distinction: Network transfer speeds are given in bits per second (e.g., $100 \text{ Mbps} = 12.5 \text{ MB/s}$), while storage sizes are given in bytes ($1 \text{ Byte} = 8 \text{ Bits}$).
3. Refresh Requirement Trap: SRAM does not need refreshing; DRAM does need periodic refreshing. Do not confuse their speed and density profiles!