9.1 ICT Terminology, Acronyms, Hardware & Memory Hierarchy

ICT Terminology, Acronyms, Hardware & Memory Hierarchy

Quick Answer: Information and Communication Technology (ICT) integrates telecommunications, computing hardware, middleware, and software systems. Computer hardware operates on the Von Neumann architecture comprising the Central Processing Unit (ALU, Control Unit, Registers), system buses (Data, Address, Control), and a structured Memory Hierarchy spanning ultra-fast CPU registers and cache down to volatile RAM (SRAM/DRAM), non-volatile ROM (PROM, EPROM, EEPROM), and magnetic/solid-state secondary storage.

1. Essential ICT Acronyms and Standard Terminology

Information and Communication Technology (ICT) encompasses the infrastructure, protocols, and digital tools utilized to capture, process, store, transmit, and present information. Standardized acronyms frequently appear in UGC NET Paper 1 examination items across four primary domains:

A. Data Representation & Character Encoding

• ASCII (American Standard Code for Information Interchange): A character encoding standard originally developed in 1963. Standard ASCII uses 7 bits to represent 128 characters ($2^7 = 128$, decimal values 0 to 127), including uppercase/lowercase Latin letters, numerals 0–9, punctuation marks, and control characters. Extended ASCII uses 8 bits ($2^8 = 256$ characters) to accommodate specialized symbols and graphical characters.
• UNICODE (Universal Character Encoding): A comprehensive, international character encoding standard maintained by the Unicode Consortium. Unlike ASCII, Unicode is designed to represent every written language, mathematical symbol, historical script, and emoji. Common variable and fixed-width formats include UTF-8 (1 to 4 bytes per character, backward compatible with 7-bit ASCII), UTF-16 (2 or 4 bytes), and UTF-32 (fixed 4 bytes / 32 bits per character).
• BCD (Binary Coded Decimal): A digital encoding method where each decimal digit (0–9) is represented by a dedicated 4-bit binary sequence (e.g., decimal 25 is encoded as 0010 0101).
• EBCDIC (Extended Binary Coded Decimal Interchange Code): An 8-bit character encoding system developed by IBM primarily for mainframe computing architectures.

B. Hardware, Firmware & Input/Output Systems

• BIOS (Basic Input/Output System): Non-volatile firmware stored in ROM/Flash memory that initializes, tests, and configures system hardware components during the power-on boot sequence via the POST (Power-On Self-Test) before handing control over to the operating system bootstrap loader.
• UEFI (Unified Extensible Firmware Interface): A modern, advanced firmware architecture that replaces legacy BIOS, offering faster boot times, support for drives larger than 2.2 TB (using GUID Partition Tables - GPT), and enhanced Secure Boot cryptographic verification.
• CMOS (Complementary Metal-Oxide-Semiconductor): A specialized on-board volatile memory chip powered by a small coin-cell lithium battery (CR2032) that preserves real-time clock (RTC) settings and hardware configuration parameters when the computer is powered off.
• GPU (Graphics Processing Unit): A specialized electronic circuit designed for massively parallel mathematical operations, optimizing 3D graphical rendering, matrix calculations, and deep learning neural network training.
• SSD (Solid State Drive): A high-speed, non-volatile secondary storage device that utilizes interconnected NAND flash memory chips with no moving mechanical parts, providing lower latency and faster read/write speeds than traditional HDDs.
• OCR (Optical Character Recognition): Optoelectronic scanning hardware and algorithmic software that converts printed, typed, or handwritten text images into machine-editable, searchable digital text.
• OMR (Optical Mark Recognition): An automated optical sensing technology that captures human-marked data from pre-printed survey forms, ballot papers, and standardized examination bubble sheets by detecting the presence or absence of light reflection/absorption.
• MICR (Magnetic Ink Character Recognition): Technology used primarily in the banking sector to read magnetic-ink characters printed on the bottom of bank cheques (containing routing numbers, account numbers, and cheque transit codes).
• QR Code (Quick Response Code): A two-dimensional (2D) matrix barcode developed in 1994 by Denso Wave, capable of storing up to 7,089 numeric or 4,296 alphanumeric characters with built-in Reed-Solomon error correction.

C. Telecommunications, Web Protocols & Networking Acronyms

• URL (Uniform Resource Locator): The global address reference format used to locate and access resources across the World Wide Web (comprising protocol, domain host, port, path, and query strings).
• URI (Uniform Resource Identifier): A generic, overarching string of characters that unambiguously identifies an abstract or physical resource.
• HTTP (Hypertext Transfer Protocol): An unencrypted application-layer client-server protocol used for transmitting hypermedia documents across the web (default TCP port 80).
• HTTPS (Hypertext Transfer Protocol Secure): Encrypted HTTP operating over Transport Layer Security (TLS/SSL) to guarantee communication confidentiality and data integrity (default TCP port 443).
• FTP (File Transfer Protocol): Standard network protocol for bidirectional file transfers between client and server (TCP port 21 for control/commands, TCP port 20 for data transfer).
• SFTP (SSH File Transfer Protocol): Secure file transfer protocol running over an encrypted Secure Shell (SSH) stream (TCP port 22).
• VoIP (Voice over Internet Protocol): Methodologies and transmission technologies for delivering real-time voice communications and multimedia sessions across Internet Protocol (IP) networks.
• ISP (Internet Service Provider): Commercial or institutional organization providing subscriber connectivity to the global Internet infrastructure.
• DNS (Domain Name System): The hierarchical, decentralized naming directory that translates human-readable hostnames (e.g., www.ugc.gov.in) into numerical IP addresses (e.g., 164.100.158.45).
• DHCP (Dynamic Host Configuration Protocol): Network management protocol that automatically assigns dynamic IP addresses, subnet masks, default gateways, and DNS server addresses to network clients.
• VPN (Virtual Private Network): An encrypted point-to-point network tunnel constructed across public telecommunication networks to ensure confidential remote data access.

D. Modern Computing Paradigms & Emerging Technologies

• IoT (Internet of Things): The interrelated network of physical objects, sensors, actuators, software, and embedded electronics capable of collecting and exchanging data over communication networks without human intervention.
• AI (Artificial Intelligence): The broad computational discipline focused on developing software systems and algorithms capable of performing cognitive tasks typically requiring human intelligence (e.g., visual perception, speech recognition, reasoning, decision-making).
• ML (Machine Learning): A core subfield of AI focused on developing statistical algorithms and predictive models that improve their performance autonomously through iterative data exposure without explicit rule programming.
• NLP (Natural Language Processing): A specialized domain of AI and computational linguistics enabling computers to parse, interpret, understand, and generate human natural languages.

2. Computer System Architecture & CPU Subsystems

Modern digital computers are grounded in the Von Neumann Architecture (introduced by mathematician John von Neumann in 1945), which features a shared memory space storing both executable program instructions and operational data (the stored-program concept).

The Central Processing Unit (CPU)

The CPU is the computational brain of the system, responsible for fetching, decoding, and executing instructions through continuous Instruction Cycles (Fetch-Decode-Execute Cycle). It comprises three primary operational subsystems:

1. Arithmetic Logic Unit (ALU):
   • Arithmetic Section: Performs fundamental mathematical operations including binary addition, subtraction, multiplication, and division.
   • Logic Section: Performs decision-making and Boolean logical evaluations (AND, OR, NOT, XOR) and relational comparisons (equal to, greater than, less than).
2. Control Unit (CU):
   • Acts as the central orchestrator and supervisor of the processor.
   • Fetches instructions sequentially from main memory, interprets the opcode (operation code) in the Instruction Register, and issues synchronized electronic control signals to coordinate data movement across the ALU, internal registers, system buses, and peripheral controllers.
   • Does not perform computational or data-storage operations directly.
3. Internal Processor Registers:
   • Ultra-fast, microscopic storage cells fabricated directly onto the silicon processor core with zero wait-state access latency.
   • Program Counter (PC): Holds the memory address of the next instruction scheduled to be fetched and executed. It increments automatically after each fetch operation.
   • Memory Address Register (MAR): Holds the memory address currently being read from or written to by the CPU via the Address Bus.
   • Memory Data Register (MDR) / Memory Buffer Register (MBR): Holds the actual data or instruction word retrieved from memory or waiting to be written into memory.
   • Instruction Register (IR): Holds the binary opcode of the instruction currently undergoing decoding and execution by the Control Unit.
   • Accumulator (AC): A general-purpose working register that stores intermediate computational results generated by the ALU.
   • Program Status Word (PSW) / Flag Register: Contains single-bit status condition flags reflecting the outcome of recent ALU operations (e.g., Zero Flag, Carry Flag, Sign Flag, Overflow Flag, Parity Flag).

The System Bus Architecture

A bus is a shared communication pathway composed of parallel electrical conducting lines that transfer binary signals between functional units:

• Address Bus (Unidirectional): Transmits memory addresses generated by the CPU to locate specific memory cells or I/O ports. The physical width of the address bus determines the maximum addressable physical memory capacity ($2^N$ bytes, where $N$ is the number of address lines; e.g., a 32-bit address bus can address $2^{32} \text{ bytes} = 4\text{ GB}$ of RAM, whereas a 64-bit address bus can address theoretical exabytes).
• Data Bus (Bidirectional): Carries actual data words and machine instructions bidirectionally between the CPU, memory, and peripheral controllers. The bus width (e.g., 32-bit, 64-bit, 128-bit) determines the volume of data transferred per bus clock cycle.
• Control Bus (Bidirectional): Transmits synchronization timing signals, operational commands, and status acknowledgments (e.g., Memory Read, Memory Write, I/O Read, I/O Write, Interrupt Requests [IRQ], Bus Grant, and Clock signals).

3. The Memory Hierarchy

The memory hierarchy is an architectural design paradigm that balances processing speed, unit cost, and physical capacity across different storage technologies. As one moves down the memory pyramid:

• Access Speed: Decreases (access latency increases from fractions of a nanosecond to milliseconds).
• Cost per Bit / Storage Density: Decreases significantly.
• Storage Capacity: Increases dramatically.
• Physical Proximity to CPU Core: Decreases.

                 /\         [ CPU Registers ]          (~0.2 - 0.5 ns, < 2 KB)
                /  \      [ Level 1 Cache (L1) ]       (~1 ns, 32 - 64 KB per core)
               /    \     [ Level 2 Cache (L2) ]       (~3 - 5 ns, 256 KB - 1 MB)
              /      \    [ Level 3 Cache (L3) ]       (~10 - 20 ns, 4 - 64 MB shared)
             /        \   [ Primary RAM / ROM  ]       (~50 - 100 ns, 8 - 128 GB)
            /          \  [ Secondary: SSD/HDD ]       (~10 µs - 10 ms, 512 GB - 16 TB)
           /____________\ [ Tertiary / Cloud   ]       (Seconds/Network latency, Petabytes)

Levels of the Hierarchy Detailed:

1. CPU Registers: The fastest, most expensive, and lowest capacity storage located directly inside the ALU/CU datapath (typical access time < 1 nanosecond).
2. Cache Memory (SRAM): High-speed buffer memory placed between the ultra-fast CPU registers and the relatively sluggish main memory to mitigate the processor-memory speed mismatch (Von Neumann bottleneck). Evaluated via the Cache Hit Ratio and Principle of Locality (Temporal and Spatial Locality):
   • L1 Cache: Split into Instruction Cache (L1i) and Data Cache (L1d); built directly into individual CPU cores; operates at core clock speed.
   • L2 Cache: Slightly larger, dedicated or semi-shared per-core cache.
   • L3 Cache: Large, multi-megabyte cache shared dynamically across all CPU processing cores on the die.
3. Primary / Main Memory (RAM & ROM): Semiconductor memory directly accessible by the CPU via the memory controller. Holds active operating system routines, running applications, and working data sets.
4. Secondary Storage (Auxiliary Storage): Non-volatile mass storage devices (NVMe SSDs, SATA SSDs, Magnetic Hard Disk Drives [HDDs]) used for persistent retention of programs, files, and operating systems.
5. Tertiary & Offline Storage: Removable media (Magnetic Tape libraries, Optical Discs: CD-ROM [~700 MB], DVD-ROM [~4.7 GB single layer, 8.5 GB dual layer], Blu-ray Disc [~25 GB single layer, 50 GB dual layer, 100 GB BDXL]) and cloud-based object storage archives.

4. Primary Memory: Volatile vs. Non-Volatile Memory

Primary memory is categorized into volatile and non-volatile technologies based on whether data persists in the absence of electrical power.

Volatile vs. Non-Volatile Memory Comparison

Static RAM (SRAM) vs. Dynamic RAM (DRAM)

Random Access Memory (RAM) allows data to be read and written in arbitrary physical order with uniform access latency. It is fabricated in two fundamental architectures:

Read-Only Memory (ROM) and Erasable Variants

ROM is non-volatile semiconductor memory primarily used to store immutable bootstrap firmware (BIOS/UEFI routines). It has evolved across multiple technical iterations:

1. Masked ROM (MROM): Hardwired at the silicon fabrication foundry with pre-programmed binary patterns. Cannot be rewritten, modified, or updated after manufacturing.
2. Programmable ROM (PROM): Manufactured as blank memory chips with microscopic electrical fuses. Programmed once by the user/technician using a specialized hardware device called a PROM Burner / Programmer via irreversible high-voltage current pulses (One-Time Programmable - OTP).
3. Erasable Programmable ROM (EPROM): Can be erased and reprogrammed multiple times. Featuring a distinctive transparent quartz crystal window on top of the ceramic package, the chip is erased by exposing it to intense Ultraviolet (UV) light (wavelength ~253.7 nm) for 15 to 30 minutes, which discharges all floating-gate transistors simultaneously (bulk erase).
4. Electrically Erasable Programmable ROM (EEPROM): Erased and reprogrammed electrically using standard operational voltage levels without requiring physical removal from the motherboard or UV light exposure. Allows byte-level erasure and rewriting (typically rated for 100,000 to 1,000,000 write/erase cycles).
5. Flash Memory: A modern, high-density specialized variant of EEPROM that reads, writes, and erases data in large contiguous blocks / sectors rather than single bytes. Flash memory forms the foundation of modern USB flash drives, SD cards, and Solid State Drives (SSDs), split into NOR Flash (fast random read, code execution) and NAND Flash (high capacity, sequential write, data storage).