12.1 Foundational ICT Terminology, Acronyms & Computer Architecture

Foundational ICT Terminology, Acronyms & Computer Architecture

Core Principle: In computer systems and digital informatics, information is represented, processed, and stored through physical voltage states mapped to binary mathematics. Mastery of data representation scales, positional number conversion algorithms, CPU microarchitecture, and memory volatility is essential for navigating modern academic technology and standardized aptitude assessments.

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1. Data Representation and the Memory Unit Hierarchy

All digital computational systems operate on binary state logic (presence or absence of electrical voltage, magnetic charge orientation, or optical pit reflection). The fundamental physical atom of digital information is the bit (binary digit), which can assume only one of two mutually exclusive discrete states: $0$ (low voltage / off) or $1$ (high voltage / on).

The Fundamental Units: Bit, Nibble, and Byte

• Bit (b): The smallest elementary unit of digital storage. A single bit can encode exactly $2^1 = 2$ unique distinct states ($0$ or $1$).
• Nibble (Half-Byte): A sequence of 4 consecutive bits. A nibble can represent $2^4 = 16$ unique binary combinations ($0000_2$ to $1111_2$). Because 16 values correspond exactly to the base of the hexadecimal number system, one nibble represents precisely one hexadecimal digit (0–9, A–F).
• Byte (B): A contiguous sequence of 8 bits. A byte represents $2^8 = 256$ distinct combinations ($00000000_2$ to $11111111_2$), spanning decimal values from 0 through 255. In computer architecture, the byte is the fundamental addressable unit of memory and the standard building block for alphanumeric characters in legacy encoding sets.
• Word: The natural data unit processed concurrently by a specific CPU architecture in a single clock cycle. Common architectures feature 32-bit (4 bytes) or 64-bit (8 bytes) word lengths. A larger word size allows the CPU to process more data per cycle and directly address exponentially larger physical memory spaces.

The Decimal ($10^3$) vs. Binary ($2^{10}$) Memory Convention

A frequent source of confusion—and a perennial exam question topic—stems from the divergence between decimal metric prefixes (standardized by the International System of Units, SI) and binary memory prefixes (standardized by the International Electrotechnical Commission, IEC):

1. Decimal Metric Scale (Powers of 10): Telecommunications engineers, data transmission networks, and secondary storage drive manufacturers define units in powers of 10: $\text{1 Kilobyte (KB)} = 10^3 \text{ Bytes} = 1{,}000 \text{ Bytes}$ $\text{1 Megabyte (MB)} = 10^6 \text{ Bytes} = 1{,}000{,}000 \text{ Bytes}$ $\text{1 Gigabyte (GB)} = 10^9 \text{ Bytes} = 1{,}000{,}000{,}000 \text{ Bytes}$ $\text{1 Terabyte (TB)} = 10^{12} \text{ Bytes} = 1{,}000{,}000{,}000{,}000 \text{ Bytes}$

2. Binary Scale (Powers of 2): In computer architecture, because address buses use binary logic, memory capacity scales in powers of 2. The binary multiple closest to 1,000 is $2^{10} = 1{,}024$. The IEC formalized these as Kibibyte (KiB), Mebibyte (MiB), and Gibibyte (GiB), though general computer operating systems still frequently label binary units using traditional KB/MB/GB abbreviations: $\text{1 Kibibyte (KiB / traditional KB)} = 2^{10} \text{ Bytes} = 1{,}024 \text{ Bytes}$ $\text{1 Mebibyte (MiB / traditional MB)} = 2^{20} \text{ Bytes} = 1{,}024 \times 1{,}024 = 1{,}048{,}576 \text{ Bytes}$ $\text{1 Gibibyte (GiB / traditional GB)} = 2^{30} \text{ Bytes} = 1{,}024^3 = 1{,}073{,}741{,}824 \text{ Bytes}$ $\text{1 Tebibyte (TiB / traditional TB)} = 2^{40} \text{ Bytes} = 1{,}024^4 = 1{,}099{,}511{,}627{,}776 \text{ Bytes}$

Exam Trap Alert: Why does a brand-new 1 Terabyte (1,000,000,000,000 Bytes) solid-state drive or hard drive show only approximately 931.32 Gigabytes when installed in Microsoft Windows? Storage manufacturers sell drive capacities based on decimal metric definitions ($10^{12}$ bytes), but operating system software computes storage capacity in binary Gibibytes ($10^{12} \div 1{,}024^3 \approx 931.32\text{ GiB}$). No storage is missing; it is purely a mathematical artifact of the decimal-versus-binary conversion discrepancy.

Comprehensive Hierarchy of Data Storage Units

Competitive examinations regularly test the precise ascending order of large-scale digital storage capacities. Candidates should know the standard hierarchy from Bit to Quettabyte:

Note: In November 2022 the 27th General Conference on Weights and Measures (CGPM) adopted the SI prefixes ronna ($10^{27}$) and quetta ($10^{30}$), so the units after the yottabyte are the ronnabyte (RB) and quettabyte (QB). Older quiz books list "brontobyte" and "geopbyte", which were never adopted as standards.

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2. Radix Number Systems and Conversion Algorithms

A radix (base) defines the total number of unique digits or symbols utilized by a positional numeral system. The value of any digit depends on both the symbol itself and its weighted position relative to the radix point.

The Four Standard Computing Number Systems

1. Binary System (Base-2): Uses digits $\{0, 1\}$. Fundamental language of physical transistor circuitry.
2. Octal System (Base-8): Uses digits $\{0, 1, 2, 3, 4, 5, 6, 7\}$. Historically used in computing because each octal digit corresponds exactly to 3 binary bits ($2^3 = 8$).
3. Decimal System (Base-10): Uses digits $\{0, 1, 2, 3, 4, 5, 6, 7, 8, 9\}$. Standard human arithmetic system.
4. Hexadecimal System (Base-16): Uses 16 alphanumeric symbols: $\{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, \text{A, B, C, D, E, F}\}$. The alphabetic characters represent numerical values from 10 to 15: $\text{A} = 10, \quad \text{B} = 11, \quad \text{C} = 12, \quad \text{D} = 13, \quad \text{E} = 14, \quad \text{F} = 15$ Because $2^4 = 16$, each hexadecimal digit corresponds exactly to a 4-bit nibble, providing a compact, human-readable shorthand for binary byte streams, memory addresses, and IPv6 configurations.

Step-by-Step Conversion Algorithms with Worked Numerical Examples

Case 1: Decimal to Binary (Successive Division by 2)

To convert an integer from decimal (base-10) to binary (base-2), divide the integer successively by 2, recording each integer quotient and remainder until the quotient reaches 0. The binary equivalent is formed by reading the remainders from bottom to top (Most Significant Bit [MSB] to Least Significant Bit [LSB]).

Worked Example: Convert $(45)_{10}$ to Binary.

• $45 \div 2 = 22$, remainder 1 (LSB)
• $22 \div 2 = 11$, remainder 0
• $11 \div 2 = 5$, remainder 1
• $5 \div 2 = 2$, remainder 1
• $2 \div 2 = 1$, remainder 0
• $1 \div 2 = 0$, remainder 1 (MSB) Reading remainders from bottom (MSB) to top (LSB): $(45)_{10} = (101101)_2$.

Case 2: Binary to Decimal (Positional Weighting)

To convert binary to decimal, multiply each binary digit $d_i$ by its positional power of 2 ($2^i$, starting with $i=0$ for the rightmost bit), then sum all products: $\text{Value} = \sum_{i=0}^{n-1} d_i \times 2^i$

Worked Example: Convert $(110101)_2$ to Decimal. $\text{Value} = (1 \times 2^5) + (1 \times 2^4) + (0 \times 2^3) + (1 \times 2^2) + (0 \times 2^1) + (1 \times 2^0)$ $\text{Value} = 32 + 16 + 0 + 4 + 0 + 1 = (53)_{10}$.

Case 3: Fractional Conversions (Successive Multiplication by 2)

For fractional decimal numbers, multiply the fraction successively by 2. The integer part of the product becomes the binary digit, and the fractional remainder is multiplied again, proceeding left-to-right.

Worked Example: Convert $(0.625)_{10}$ to Binary.

• $0.625 \times 2 = \mathbf{1}.25 \implies$ integer digit 1 (MSB)
• $0.25 \times 2 = \mathbf{0}.50 \implies$ integer digit 0
• $0.50 \times 2 = \mathbf{1}.00 \implies$ integer digit 1 (terminates) Reading integers from top to bottom: $(0.625)_{10} = (0.101)_2$. Combining whole and fractional parts: $(45.625)_{10} = (101101.101)_2$.

Case 4: Binary to Hexadecimal (Direct 4-Bit Grouping)

Because $16 = 2^4$, conversion between binary and hexadecimal requires no division. Group the binary string into clusters of 4 bits starting from the radix point (moving left for integers, padding leading zeros if necessary; moving right for fractions, padding trailing zeros). Replace each 4-bit nibble with its hexadecimal symbol.

Worked Example: Convert $(111010110010)_2$ to Hexadecimal.

• Partition into 4-bit nibbles: 1110 | 1011 | 0010
• Convert 1110 to decimal: $8 + 4 + 2 + 0 = 14 \implies \mathbf{E}$
• Convert 1011 to decimal: $8 + 0 + 2 + 1 = 11 \implies \mathbf{B}$
• Convert 0010 to decimal: $0 + 0 + 2 + 0 = 2 \implies \mathbf{2}$ Result: $(111010110010)_2 = (\text{EB}2)_{16}$.

Case 5: Decimal to Hexadecimal (Successive Division by 16)

Divide the decimal number successively by 16, noting remainders, and map remainders $\ge 10$ to letters A–F.

Worked Example: Convert $(754)_{10}$ to Hexadecimal.

• $754 \div 16 = 47$, remainder 2 (LSB)
• $47 \div 16 = 2$, remainder $15 \implies \mathbf{F}$
• $2 \div 16 = 0$, remainder 2 (MSB) Reading from bottom to top: $(754)_{10} = (2\text{F}2)_{16}$.

Character Encoding Schemes

Computers encode text by mapping characters to numeric binary bit patterns.

1. ASCII (American Standard Code for Information Interchange):

   • Standard 7-bit ASCII: First published in 1963 by the American Standards Association (ASA, now ANSI). Encodes $2^7 = 128$ distinct characters (codes 0 to 127), including 33 non-printable control characters (such as Null, Carriage Return, Line Feed) and 95 printable characters (English alphabet A–Z, a–z, digits 0–9, punctuation).
   • Key Decimal Anchor Values (Frequently Tested):
     • Character '0' to '9' $\implies$ Decimal 48 to 57 (Binary 00110000 to 00111001)
     • Uppercase 'A' to 'Z' $\implies$ Decimal 65 to 90 ('A' = 65, 'B' = 66, ..., 'Z' = 90)
     • Lowercase 'a' to 'z' $\implies$ Decimal 97 to 122 ('a' = 97, 'b' = 98, ..., 'z' = 122)
     • Diagnostic Observation: The numerical difference between any uppercase letter and its lowercase counterpart is exactly 32 ($97 - 65 = 32$). In binary, toggling the 6th bit (weight 32, bit index 5) converts between uppercase and lowercase.
   • Extended 8-bit ASCII: Utilizes all 8 bits of a byte ($2^8 = 256$ characters, codes 0 to 255). Retains standard ASCII for codes 0–127 and adds codes 128–255 for accented Latin characters, mathematical symbols, and graphical box-drawing borders.

2. ISCII (Indian Script Code for Information Interchange):

   • Developed in 1988 under the Department of Electronics and adopted by the Bureau of Indian Standards (BIS) as IS 13194:1991, an 8-bit character encoding specifically designed to encode Indian regional scripts (Devanagari, Bengali, Gurmukhi, Gujarati, Oriya, Tamil, Telugu, Kannada, Malayalam, and Assamese).
   • Retains standard 7-bit ASCII in the lower half (codes 0–127) for English compatibility, while allocating the upper 128 codes (128–255) for Indian phonetic alphabets. Because all major Indian scripts share a common Brahmi origin, ISCII maps equivalent phonemes across different regional scripts to the same code point.

3. Unicode (Universal Coded Character Set):

   • A modern international computing standard maintained by the Unicode Consortium designed to encode every written character in human linguistic history, as well as emojis and mathematical symbols, with a repertoire that grows with each new version (now more than 150,000 characters across over 160 modern and historic scripts).
   • UTF-8 (Unicode Transformation Format, 8-bit): Variable-length encoding using 1 to 4 bytes per character. Crucially, UTF-8 is 100% backward-compatible with 7-bit ASCII; all ASCII characters are represented as single bytes with identical values (0–127). It powers over 98% of the World Wide Web.
   • UTF-16: Variable-length encoding using 2 or 4 bytes per code point. Widely adopted as the internal memory encoding for modern operating system runtimes (Microsoft Windows, Java Virtual Machine, JavaScript engines).
   • UTF-32: Fixed-length encoding using exactly 4 bytes (32 bits) per character. Fast random indexing in memory, but quadruples storage requirements for standard Latin text.

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3. Computer Hardware Architecture: The Von Neumann Model

In 1945, mathematician and physicist John von Neumann published First Draft of a Report on the EDVAC, formulating the theoretical architecture that underpins virtually all contemporary general-purpose computers.

                        VON NEUMANN ARCHITECTURE
       ┌────────────────────────────────────────────────────────┐
       │              CENTRAL PROCESSING UNIT (CPU)             │
       │  ┌───────────────────────┐   ┌──────────────────────┐  │
       │  │ Control Unit (CU)     │   │ Registers (PC, MAR,  │  │
       │  │ - Instruction Decoder │   │  MDR, IR, AC, etc.)  │  │
       │  └───────────┬───────────┘   └──────────┬───────────┘  │
       │              │                          │              │
       │  ┌───────────┴──────────────────────────┴───────────┐  │
       │  │ Arithmetic Logic Unit (ALU)                      │  │
       │  └──────────────────────────────────────────────────┘  │
       └──────────────────────────┬─────────────────────────────┘
                                  │ (System Bus: Control, Address, Data)
       ┌──────────────────────────┴─────────────────────────────┐
       │           SHARED PRIMARY MEMORY (RAM / ROM)            │
       │        [Stored Instructions]  &  [Data Operands]       │
       └──────────────────────────┬─────────────────────────────┘
                                  │
       ┌──────────────────────────┴─────────────────────────────┐
       │                   INPUT / OUTPUT UNITS                 │
       │       (Keyboard, Mouse, Display, Network, Storage)     │
       └────────────────────────────────────────────────────────┘

Core Pillars of the Von Neumann Architecture

1. The Stored-Program Concept: Instructions (code) and operands (data) are stored together in the same unified, read-write primary memory space. The CPU treats instructions and data identically as binary byte sequences; only the execution context distinguishes them.
2. Sequential Instruction Processing: Instructions are fetched and executed in strict sequential order from contiguous memory addresses, unless interrupted or redirected by a branch, jump, or conditional instruction.
3. Central Processing Unit (CPU): Comprises three primary sub-systems:
   • Arithmetic Logic Unit (ALU): The execution engine that executes elementary arithmetic operations (addition, subtraction, multiplication, division) and logical decisions (AND, OR, NOT, XOR, bitwise shifts, and numerical magnitude comparisons).
   • Control Unit (CU): The central nervous system of the CPU. It directs the internal traffic of data, orchestrates the multi-phase machine instruction cycle, and generates electrical synchronization control signals sent across the system bus.
   • High-Speed Internal Registers: Extremely fast, small physical storage circuits located directly on the CPU silicon die to hold operands, addresses, and intermediate computation states.

Crucial CPU Registers and Their Functions

• Program Counter (PC): Holds the memory address of the next instruction scheduled to be fetched and executed. Automatically increments after each fetch cycle unless modified by a jump or subroutine call.
• Memory Address Register (MAR): Holds the physical memory address currently being read from or written to over the address bus.
• Memory Data Register (MDR) / Memory Buffer Register (MBR): Holds the actual data or instruction word fetched from memory, or waiting to be written into memory.
• Instruction Register (IR): Holds the current binary instruction opcode fetched from memory while the Control Unit decodes it.
• Accumulator (AC): A general-purpose working register that stores the immediate results of arithmetic and logical operations produced by the ALU.
• Current Status / Flag Register: Contains individual status bits (flags) indicating the mathematical outcomes of the latest ALU operation (Zero Flag [Z], Carry Flag [C], Overflow Flag [V], Sign/Negative Flag [S]).

The System Bus Architecture

Communication between the CPU, primary memory, and peripheral controllers is mediated by three physical groups of parallel wires known collectively as the System Bus:

1. Data Bus: Bidirectional highway that carries actual data, operands, and instructions between the CPU and memory/devices. The width of the data bus (e.g., 32 bits, 64 bits) dictates how much data the CPU can transfer in a single cycle.
2. Address Bus: Unidirectional highway driven exclusively by the CPU to designate the specific physical memory location or I/O port being accessed. Crucial Math Formula: The width of the address bus determines the CPU's maximum addressable memory capacity. If an address bus has $k$ lines (bits), it can address precisely $2^k$ distinct byte locations: $\text{32-bit address bus} \implies 2^{32} \text{ bytes} = 4{,}294{,}967{,}296 \text{ bytes} = 4 \text{ GiB}$ $\text{64-bit address bus} \implies 2^{64} \text{ bytes} = 16 \text{ Exbibytes (EiB)}$
3. Control Bus: Bidirectional lines transmitting timing, status, and synchronization signals (Memory Read, Memory Write, I/O Read, Bus Request, Bus Acknowledge, Interrupt Requests [IRQ], and System Clock).

The Von Neumann Bottleneck: Because instructions and data must share the exact same physical bus to travel between primary memory and the CPU, throughput is physically capped by the memory bus bandwidth. The CPU frequently sits idle waiting for instructions or operands to arrive from relatively slow main memory. Modern processor designs mitigate this bottleneck through multi-level internal SRAM cache hierarchies, instruction prefetching, and pipelining.

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4. Memory Hierarchy: Latency, Volatility, and Architecture

Computer storage is organized into a rigid hierarchical pyramid to balance three conflicting physical engineering realities: speed (latency), cost per bit, and capacity.

                       THE MEMORY HIERARCHY
                           /          \
                          /  REGISTERS \
                         /   (< 1 ns)   \
                        /────────────────\
                       /    L1/L2/L3      \
                      /    SRAM CACHE      \
                     /     (1 - 10 ns)      \
                    /────────────────────────\
                   /    PRIMARY MAIN MEMORY   \
                  /    DRAM (RAM) / ROM BIOS   \
                 /          (10 - 50 ns)        \
                /────────────────────────────────\
               /        SECONDARY STORAGE         \
              /    Solid State (NVMe/SATA SSD)     \
             /     Hard Disk Drives (HDD) (ms)      \
            /────────────────────────────────────────\
           /             TERTIARY & CLOUD             \
          /       Magnetic Tape, Optical Storage,      \
         /          Cloud Archival Repositories        \
        /────────────────────────────────────────────────\
        SPEED / COST INCREASES ▲  │  ▼ CAPACITY INCREASES

Volatile vs. Non-Volatile Memory

• Volatile Memory: Storage media that requires continuous electrical power to sustain its stored contents. When power is severed or interrupted, all stored binary data is instantaneously and irreversibly lost. Examples: CPU Registers, L1/L2/L3 Cache (SRAM), and System Main Memory (DRAM).
• Non-Volatile Memory: Storage media that preserves its stored data indefinitely in the complete absence of electrical power. Examples: Read-Only Memory (ROM), Flash Memory (SSDs, USB thumb drives), magnetic hard drives, magnetic tapes, and optical discs.

Primary Random Access Memory (RAM): SRAM vs. DRAM

Competitive examinations frequently require candidates to contrast the two technological forms of volatile semiconductor RAM:

Evolution of Read-Only Memory (ROM) and Firmware

Non-volatile primary memory stores the foundational startup firmware (BIOS / UEFI) required to perform the Power-On Self-Test (POST) and bootstrap the operating system from secondary storage into RAM:

1. Mask ROM (MROM): Hardwired at the semiconductor foundry during physical fabrication. The binary data pattern is etched permanently into the silicon mask. Completely unalterable and immune to reprogramming.
2. PROM (Programmable ROM): Manufactured in a blank state with tiny internal microscopic fusible links. The user or engineer writes data once using a high-voltage specialized device called a PROM programmer or "ROM burner" which permanently blows open specific fuses. One-Time Programmable (OTP); cannot be erased or rewritten once programmed.
3. EPROM (Erasable Programmable ROM): Distinguishable by a transparent circular quartz crystal window on top of the ceramic chip packaging. When exposed to intense high-frequency ultraviolet (UV) light for 20 to 30 minutes, photon energy excites electrons trapped on floating gates, erasing all stored data simultaneously. The chip can then be electrically reprogrammed. It must be physically removed from the circuit board to be erased.
4. EEPROM (Electrically Erasable Programmable ROM): Erased and reprogrammed using electrical voltage pulses without removing the chip from the computer motherboard. Crucially, EEPROM permits byte-level electrical modification, allowing individual configuration bytes to be updated without wiping the entire chip. It has finite write endurance (typically 100,000 to 1,000,000 write cycles).
5. Flash Memory: A modern high-density variation of EEPROM developed by Toshiba in the 1980s. Unlike traditional EEPROM which can erase byte-by-byte, Flash memory erases data in large multi-kilobyte blocks or sectors, achieving vastly higher density and write speeds. It represents the foundational technology powering Solid State Drives (SSDs), USB flash thumb drives, SD cards, and modern UEFI BIOS motherboard chips:
   • NOR Flash: Allows true random byte-level read access, making it ideal for storing processor execution code directly (Execute-in-Place / XIP firmware chips).
   • NAND Flash: Sacrifices byte-level random access in favor of high-density page/block sequential access, providing ultra-compact, high-capacity secondary storage for consumer SSDs and mobile devices.

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5. Master Glossary of High-Yield ICT Abbreviations

The following comprehensive reference table compiles every foundational ICT abbreviation tested in state and national eligibility examinations, organized alphabetically with precise definitions: