5.2 Combinational & Sequential Logic

Combinational vs sequential logic

The FE exam separates digital circuits into two families. Combinational logic produces an output that depends only on the present input combination, with no memory; AND, OR, and decoder networks are combinational. Sequential logic adds memory elements, so the output depends on both the present inputs and the stored state, and it is synchronized by a clock.

Recognizing which family a problem belongs to tells you whether to write a truth table (combinational) or a state/transition analysis (sequential). Gates are the atoms of both.

Basic gate truth table

Know these by heart; the FE rarely supplies them in the time you have.

XOR (exclusive OR) is 1 only when the inputs differ, which makes it the core of adders and parity circuits. NAND is 0 only when all inputs are 1, and along with NOR it is universal: any logic function can be built from NAND gates alone.

Combinational building blocks

FE questions reuse a small set of standard combinational modules:

• Multiplexer (MUX): routes one of n data inputs to a single output, chosen by log2(n) select lines. A 4-to-1 MUX needs 2 select lines.
• Demultiplexer: the reverse, steering one input to one of several outputs.
• Decoder: turns an n-bit code into one active line out of 2^n. A 3-to-8 decoder activates exactly one of eight outputs.
• Encoder: the reverse of a decoder, producing an n-bit code from an active input line.
• Adder: a full adder sums two bits plus a carry-in, producing a sum and carry-out; chaining them builds a ripple-carry adder.

A MUX can also implement any Boolean function directly, which is a favorite exam shortcut.

Flip-flops: the storage element

A flip-flop stores one bit and updates on a clock edge. The exam expects the behavior of three types:

• D flip-flop: Q takes the value of D at the active clock edge. Simple, predictable, the default storage cell.
• JK flip-flop: J=K=0 holds, J=1/K=0 sets, J=0/K=1 resets, and J=K=1 toggles Q.
• T flip-flop: toggles Q each clock edge when T=1, which makes it the natural counter element.

Latches are level-sensitive while flip-flops are edge-triggered; the FE usually means edge-triggered devices when it says 'flip-flop'. Setup and hold times define the window around the clock edge during which the data input must stay stable.

Registers, counters, and state machines

Grouping flip-flops gives larger sequential blocks. A register is a set of flip-flops sharing a clock that stores a multi-bit word; a shift register moves bits one position per clock for serial-to-parallel conversion. A counter sequences through states: an n-bit binary counter has 2^n states, so a mod-10 (decade) counter needs 4 flip-flops plus logic to reset at the count of ten.

A finite-state machine (FSM) generalizes all of this with states, transitions, and outputs. The FE distinguishes two styles:

• Moore machine: outputs depend only on the current state, so outputs change only at clock edges and are glitch-resistant.
• Mealy machine: outputs depend on the current state and the present inputs, so it often needs fewer states but its outputs can change between clock edges.