5.2 Combinational & Sequential Logic

Combinational vs sequential logic

The FE separates digital circuits into two families. Combinational logic produces an output that depends only on the present input combination, with no memory; AND/OR networks, multiplexers, decoders, and adders are combinational and are analyzed with a truth table. Sequential logic adds memory elements, so the output depends on both present inputs and stored state, and it is synchronized by a clock; it is analyzed with a state/transition table.

Recognizing the family tells you the right tool: write a truth table for combinational problems, and a state diagram or excitation table for sequential ones. Gates are the atoms of both.

Basic gate truth table

Know these by heart; the FE rarely gives you time to derive them.

XOR is 1 only when the inputs differ, which makes it the core of adders and parity circuits. NAND is 0 only when all inputs are 1; with NOR it is universal, so any logic function can be built from NAND gates alone. XNOR (not shown) is the complement of XOR and equals 1 when inputs match - an equality detector.

Combinational building blocks

FE questions reuse a small set of standard combinational modules:

• Multiplexer (MUX): routes one of n data inputs to a single output, chosen by log2(n) select lines. A 4-to-1 MUX needs 2 select lines; an 8-to-1 needs 3. A MUX can implement any Boolean function directly - a favorite exam shortcut.
• Demultiplexer: the reverse, steering one input to one of several outputs.
• Decoder: turns an n-bit code into one active line out of 2^n; a 3-to-8 decoder activates exactly one of eight outputs.
• Encoder: the reverse of a decoder, producing an n-bit code from an active input.
• Half adder: sums two bits, S = A XOR B, carry = A AND B.
• Full adder: sums two bits plus carry-in; chaining n full adders builds a ripple-carry adder, whose worst-case delay grows with n as the carry propagates.

Worked combinational example: a 4-to-1 MUX has data inputs D0-D3 and select lines S1,S0. When S1S0 = 10 (binary 2), the output equals D2; the Boolean form is Y = S1'S0'D0 + S1'S0 D1 + S1 S0' D2 + S1 S0 D3. To implement a 3-input function on a 4-to-1 MUX, drive the two select lines with two of the variables and wire each data input to 0, 1, the third variable, or its complement as the truth table requires.

Latches and flip-flops: the storage element

A latch is level-sensitive (transparent while the enable is high); a flip-flop is edge-triggered (samples only at the clock edge). The FE usually means edge-triggered when it says 'flip-flop.' Expect the behavior of four cells:

• SR latch: S=1 sets Q=1, R=1 resets Q=0; S=R=1 is forbidden (indeterminate).
• D flip-flop: Q takes the value of D at the active clock edge - the simple default storage cell.
• JK flip-flop: J=K=0 holds, J=1/K=0 sets, J=0/K=1 resets, J=K=1 toggles Q.
• T flip-flop: toggles Q each edge when T=1 - the natural counter element (a JK with J=K tied together).

Setup time and hold time define the window around the clock edge during which D must stay stable; violating them causes metastability.

Registers, counters, and state machines

Grouping flip-flops builds larger sequential blocks. A register is a set of flip-flops sharing a clock that stores a multi-bit word; a shift register moves bits one position per clock for serial-to-parallel conversion. A counter sequences through states: an n-bit binary counter has 2^n states.

Worked counter: Build a mod-10 (decade) counter. You need enough flip-flops so 2^n is at least 10: n=3 gives only 8 (too few), n=4 gives 16 (enough). So 4 flip-flops count 0000 through 1001, and a small decode (detect 1010) resets the counter back to 0000, truncating the natural 16-state cycle to 10.

A ripple (asynchronous) counter chains each flip-flop's output to the next stage's clock, so carries ripple and the count glitches briefly; a synchronous counter clocks all flip-flops from one common clock for cleaner, faster timing and is preferred in design. The maximum clock rate of any sequential circuit is set by the longest register-to-register path: clock period >= propagation delay + combinational logic delay + setup time, and that constraint is what a timing question is really testing.

Mealy vs Moore finite-state machines

A finite-state machine (FSM) generalizes sequential logic with states, transitions, and outputs.

Moore outputs are registered and glitch-resistant; Mealy outputs react one clock sooner and may use fewer states. The FE asks you to classify a diagram: if outputs are written inside state bubbles it is Moore; if outputs are written on the transition arrows it is Mealy.