Section 2.2: Combinational & Sequential Logic

2.2 Combinational & Sequential Logic

Digital logic is divided into two primary categories: combinational logic and sequential logic. Understanding the distinction between these two concepts is fundamental to maintaining and troubleshooting automated hardware.

• In combinational logic circuits, the output at any given instant depends solely on the current combination of inputs. There is no memory, no feedback paths, and no dependence on previous states. Examples include adders, multiplexers, and decoders.
• In sequential logic circuits, the output depends not only on the current inputs but also on the history of previous inputs. Sequential circuits possess memory, typically utilizing feedback loops and a clock signal to synchronize state transitions. Examples include flip-flops, counters, and registers.

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Combinational Logic Devices

Combinational devices are the decision-making nodes of digital systems. Two of the most common combinational components are multiplexers and decoders.

Multiplexer (MUX)

A multiplexer (often abbreviated as MUX), or data selector, is a circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. A MUX with 2^n data inputs requires n selection lines.

For example, a 2-to-1 MUX has two data inputs (I0, I1), one select line (S), and one output (Y).

• If S = 0, the output Y = I0.
• If S = 1, the output Y = I1.

Multiplexers are used extensively for routing data, implementing parallel-to-serial conversion, and sharing a single communication channel among multiple sensors in postal scanning equipment.

Decoder

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2^n unique output lines. Only one output line is active at a time, corresponding to the binary value represented by the inputs.

For example, a 2-to-4 line decoder takes a 2-bit binary input (00, 01, 10, or 11) and activates one of four corresponding output lines (Y0, Y1, Y2, or Y3).

• If inputs are 00, Y0 is active.
• If inputs are 01, Y1 is active.
• If inputs are 10, Y2 is active.
• If inputs are 11, Y3 is active.

Decoders are widely used for memory address decoding in microprocessors (selecting a specific memory chip or peripheral based on the address bus) and in driving numeric displays, such as binary-coded decimal (BCD) to seven-segment decoders.

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Sequential Logic and Memory Elements

Sequential logic relies on bistable memory devices that can hold their state until commanded to change.

Latch vs. Flip-Flop

Both latches and flip-flops are bistable multivibrators (devices with two stable states). The key difference lies in how they are triggered:

• Latch: Level-sensitive. The output can change state at any time the enable signal is active (transparent mode).
• Flip-Flop: Edge-triggered. The output updates only at a specific transition of a clock signal—either the rising (positive) edge or the falling (negative) edge.

Clock Timing Parameters

To ensure reliable operation, digital inputs must be stable around the clock edge:

• Setup Time: The minimum duration the input data must remain stable before the active clock edge arrives.
• Hold Time: The minimum duration the input data must remain stable after the active clock edge has passed.

If these timing windows are violated, the flip-flop can enter metastability, an unstable state where the output hovers between 0 and 1 before settling. This leads to unpredictable system behavior and control errors.

Flip-Flop Types and Truth Tables

1. SR Flip-Flop (Set-Reset)

The SR flip-flop has two inputs: Set (S) and Reset (R).

• If S = 1, R = 0 -> Q = 1 (Set)
• If S = 0, R = 1 -> Q = 0 (Reset)
• If S = 0, R = 0 -> Output Q remains unchanged (Hold)
• If S = 1, R = 1 -> Invalid State (Both Q and Q-bar try to go low, leading to erratic behavior when inputs are removed).

2. D Flip-Flop (Data)

The D flip-flop eliminates the invalid state of the SR flip-flop by connecting the S and R inputs together through an inverter. It has a single data input (D) and a clock. On the active clock edge, the logic level at D is transferred directly to the output Q. It acts as a single-bit storage latch.

3. JK Flip-Flop

The JK flip-flop is a universal flip-flop that resolves the invalid state of the SR flip-flop.

• J acts as Set; K acts as Reset.
• If J = 1 and K = 1, the output toggles (inverts its state: Q becomes Q') on the active clock edge.

4. T Flip-Flop (Toggle)

A T flip-flop has a single input (T). If T = 1, the output toggles on every clock edge. If T = 0, the output remains unchanged. T flip-flops act as binary frequency dividers (the output frequency is exactly half of the input clock frequency).

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Counters

Counters are sequential circuits designed to cycle through a predetermined sequence of binary states.

• Asynchronous Counter (or Ripple Counter): The clock pulse is applied only to the first flip-flop. The output of each flip-flop acts as the clock input for the next stage. Because each stage has a small propagation delay, these delays accumulate down the line. This "ripple" effect can cause temporary incorrect states (glitches) and limits the maximum count frequency.
• Synchronous Counter: The common clock line is connected to all flip-flops simultaneously. All stages toggle at the exact same instant, eliminating accumulation of propagation delays. This allows for reliable high-speed operation but requires more complex gating logic.

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Shift Registers

A shift register is a sequential circuit consisting of a chain of flip-flops connected in series. It is used to store and shift binary data on each clock pulse. The four primary data-shifting modes are:

1. Serial-In Serial-Out (SISO): Data is loaded one bit at a time and read out one bit at a time. Used for signal delay lines.
2. Serial-In Parallel-Out (SIPO): Data is loaded one bit at a time. Once loaded, all bits are read simultaneously from the parallel outputs. Used to convert serial communications to parallel buses.
3. Parallel-In Serial-Out (PISO): Data is loaded in parallel all at once, then shifted out one bit at a time. Used in serial transmitters.
4. Parallel-In Parallel-Out (PIPO): Data is loaded in parallel and read out in parallel. Used for high-speed buffering in registers.