9.1 IEC 61131-3 Programming Languages: LD, FBD, ST, SFC and Legacy IL

IEC 61131-3 Programming Languages: LD, FBD, ST, SFC, and IL

In Domain 4 (Development) of the ISA Certified Automation Professional body of knowledge, translating operational requirements and control narratives into deterministic, maintainable, and verifiable code is a core engineering competency. Prior to international standardization, programmable logic controller (PLC) programming was characterized by proprietary vendor dialects, non-standard memory addressing, and incompatible instruction sets.

The publication of IEC 61131-3 (Programmable controllers – Part 3: Programming languages) established a vendor-independent software architecture, standardized data typing, and a common set of programming languages. The current fourth edition (May 2025) defines Ladder Diagram, Function Block Diagram and Structured Text plus Sequential Function Chart elements; the older Instruction List language was deprecated in 2013 and removed in 2025, although some vendor tools still support it. An automation professional must master the architectural model of IEC 61131-3, understand the execution semantics of each language, and select the appropriate programming paradigm to suit the physical dynamics of the process.

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IEC 61131-3 Architectural Software Model

IEC 61131-3 defines a structured, top-down software architecture that abstracts hardware dependencies while providing deterministic execution control.

+-------------------------------------------------------------------------+
| CONFIGURATION (e.g., Complete PAC Rack / Modular PLC System)            |
|                                                                         |
|   +-----------------------------------------------------------------+   |
|   | RESOURCE 1 (Processor CPU Module A)                             |   |
|   |   +---------------------------------------------------------+   |   |
|   |   | TASK 1 (Periodic: 10 ms, Priority 1 - High-Speed Fast)   |   |   |
|   |   |   - Program 1 (Motion_Axis_Coordination)                |   |   |
|   |   +---------------------------------------------------------+   |   |
|   |   +---------------------------------------------------------+   |   |
|   |   | TASK 2 (Periodic: 100 ms, Priority 5 - Regulatory Loops) |   |   |
|   |   |   - Program 2 (Distillation_Pressure_Control)           |   |   |
|   |   +---------------------------------------------------------+   |   |
|   |   +---------------------------------------------------------+   |   |
|   |   | TASK 3 (Continuous / Event-Driven, Priority 10 - Comms) |   |   |
|   |   |   - Program 3 (SCADA_Data_Concentrator)                 |   |   |
|   |   +---------------------------------------------------------+   |   |
|   |   [Global Variables & Hardware I/O Mapping Engine]          |   |   |
|   +-----------------------------------------------------------------+   |
|                                                                         |
|   +-----------------------------------------------------------------+   |
|   | RESOURCE 2 (Processor CPU Module B - Co-processor / Safety Core)|   |
|   |   +---------------------------------------------------------+   |   |
|   |   | TASK 4 (Periodic: 20 ms, SIL 3 Safety Logic)            |   |   |
|   |   |   - Program 4 (Emergency_Depressurization_SIS)          |   |   |
|   |   +---------------------------------------------------------+   |   |
|   +-----------------------------------------------------------------+   |
+-------------------------------------------------------------------------+

Core Structural Elements

1. Configuration: Represents the highest-level language element, corresponding to a complete programmable controller system (e.g., an entire chassis, industrial PC, or distributed control node).
2. Resource: Corresponds to an autonomous processing facility within a Configuration that contains its own execution control and memory (e.g., an individual CPU core or co-processor plug-in module).
3. Task: A scheduling mechanism that governs execution timing and priorities for one or more programs. Tasks are configured as either Periodic/Cyclic (invoked at fixed millisecond intervals, such as 10 ms or 100 ms) or Event-Driven (triggered by hardware interrupts, diagnostic faults, or external communication events). Tasks are assigned numeric priorities; when an interrupt fires, the preemptive real-time operating system (RTOS) pauses lower-priority tasks to execute higher-priority logic deterministically.
4. Program Organization Units (POUs): The modular blocks containing user application code. The three classic POU types are shown below; the third edition (2013) added object-oriented classes, and the fourth edition (2025) added features such as properties, mutexes and semaphores for multicore task synchronization, and UTF-8 strings.

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Data Typing and Memory Structures

IEC 61131-3 enforces strong data typing to prevent illegal arithmetic operations, silent memory overflow, and undefined type coercions during execution.

Elementary Data Types

• Bit Strings: BOOL (1-bit logical), BYTE (8-bit), WORD (16-bit), DWORD (32-bit), LWORD (64-bit).
• Signed Integers: SINT (Short Integer, 8-bit, $-128 \text{ to } 127$), INT (Standard Integer, 16-bit, $-32{,}768 \text{ to } 32{,}767$), DINT (Double Integer, 32-bit, $-2{,}147{,}483{,}648 \text{ to } 2{,}147{,}483{,}647$), LINT (Long Integer, 64-bit).
• Unsigned Integers: USINT (0 to 255), UINT (0 to 65,535), UDINT (0 to $4{,}294{,}967{,}295$), ULINT (64-bit unsigned).
• Floating Point: REAL (32-bit IEEE 754 single-precision, $\approx 7$ decimal digits of precision), LREAL (64-bit IEEE 754 double-precision, $\approx 15$ decimal digits of precision).
• Time and Duration: TIME (e.g., T#2h45m12s500ms), DATE (e.g., D#2026-10-12), TIME_OF_DAY / TOD (e.g., TOD#14:30:00.00), DATE_AND_TIME / DT.
• Characters and Strings: STRING (variable-length 8-bit ASCII), WSTRING (16-bit Unicode characters).

Derived and Complex Data Types

Programmers can construct customized data architectures tailored to physical process assets:

• Arrays: Homogeneous collections indexed by integer ranges, such as RawTemperatures : ARRAY [1..64] OF REAL;.
• Structures (STRUCT): Heterogeneous groupings encapsulating an entire field device profile:

TYPE Motor_Profile : 
STRUCT
    Run_Command       : BOOL;
    Aux_Contact_Run   : BOOL;
    Fault_Tripped     : BOOL;
    Operating_Hours   : DINT;
    Motor_Current_Amps: REAL;
    Speed_Setpoint_RPM: REAL;
END_STRUCT;
END_TYPE

• Enumerations (ENUM): Named discrete states that prevent ambiguous integer tags:

TYPE Valve_State : (VALVE_CLOSED, VALVE_OPENING, VALVE_OPEN, VALVE_CLOSING, VALVE_FAULT);
END_TYPE

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The IEC 61131-3 Programming Languages

Historically, IEC 61131-3 defined two graphical languages (LD and FBD), two textual languages (ST and IL) and the Sequential Function Chart structuring language. The 2025 edition drops IL, leaving LD, FBD, ST and SFC; IL is still worth recognizing because a large amount of legacy code uses it.

+-------------------------------------------------------------------------+
|                        IEC 61131-3 LANGUAGE SPECTRUM                    |
|                                                                         |
|   GRAPHICAL PARADIGMS                    TEXTUAL PARADIGMS              |
|   +-------------------------------+      +--------------------------+   |
|   | Ladder Diagram (LD)           |      | Structured Text (ST)     |   |
|   | - Rungs, Contacts, Coils      |      | - High-level Pascal-like |   |
|   | - Discrete interlocks/relays  |      | - Complex math, loops    |   |
|   +-------------------------------+      +--------------------------+   |
|   | Function Block Diagram (FBD)  |      | Instruction List (IL)    |   |
|   | - Graphical signal flow       |      | - Low-level accumulator  |   |
|   | - PID, filters, math blocks   |      | - (Removed in 2025 ed.)  |   |
|   +-------------------------------+      +--------------------------+   |
|                                                                         |
|   SEQUENTIAL COORDINATION                                               |
|   +-----------------------------------------------------------------+   |
|   | Sequential Function Chart (SFC)                                 |   |
|   | - Steps, Transitions, Action Qualifiers (N, S, R, P, L, D)      |   |
|   | - Batch unit procedures, recipe phase coordination (ISA-88)     |   |
|   +-----------------------------------------------------------------+   |
+-------------------------------------------------------------------------+

1. Ladder Diagram (LD)

Ladder Diagram emulates hardwired electromechanical relay schematics. It consists of two vertical power rails (left energized rail and right return rail) interconnected by horizontal rungs of logic.

• Execution Semantics: Solved left-to-right across each rung, and top-to-bottom sequentially through the routine. Power flows conceptually across contacts to energize output coils.
• Language Elements:
  • Normally Open Contact (--[ ]--): Passes power if the referenced bit is TRUE (1).
  • Normally Closed Contact (--[/]--): Passes power if the referenced bit is FALSE (0).
  • Edge Transition Contacts: Positive transition (--[P]--) passes power for exactly one scan upon a 0-to-1 transition; Negative transition (--[N]--) passes power on a 1-to-0 transition.
  • Standard Output Coil (--( )--): Sets referenced bit TRUE if rung power condition is satisfied; sets bit FALSE if rung condition is false.
  • Latch / Set Coil (--(S)-- or --(L)--): Sets bit TRUE when energized; bit remains latched TRUE even when rung power is subsequently lost.
  • Unlatch / Reset Coil (--(R)-- or --(U)--): Sets bit FALSE when energized, clearing an active latch.

LADDER DIAGRAM REPRESENTATION (Motor Seal-In Logic):

 Power                                                            Power
 Rail                                                             Rail
  |   E_Stop_OK     Overload_OK    Stop_PB       Start_PB          |
  |------[ ]-----------[ ]-----------[ ]----+------[ ]------+--( )--|
  |                                         |               | Motor |
  |                                         |  Motor_Aux    |       |
  |                                         +------[ ]------+       |
  |                                                                 |

2. Function Block Diagram (FBD)

Function Block Diagram is a graphical language rooted in electronic circuit design and signal processing. Logic elements appear as interconnected rectangular functional blocks with input parameters on the left and output parameters on the right.

• Execution Semantics: Continuous data-flow model. A block executes when its inputs are available, transmitting its outputs down connecting signal wires to downstream blocks. In modern PAC compilers, execution order is determined by signal dependency or explicitly configured block execution sequence numbers.
• Application Strengths: Continuous regulatory control, analog signal conditioning, transmitter lead/lag filtering, feedforward summation, and PID cascade loops.

FUNCTION BLOCK DIAGRAM (Lead/Lag Filter with Saturation Limit):

   +-------------+       +--------------+       +--------------+
   |  LEAD_LAG   |       |  GAIN_OFFSET |       |  SATURATION  |
---| IN     OUT  |=======| IN      OUT  |=======| IN       OUT |---> (To Valve)
   | LEAD   TC1  |       | GAIN    BIAS |       | HI_LIM       |
   | LAG    TC2  |       +--------------+       | LO_LIM       |
   +-------------+                              +--------------+

3. Structured Text (ST)

Structured Text is an advanced, high-level, block-structured language modeled on Pascal and Ada. It provides mathematical notation, programmatic iteration, and nested conditional constructs.

• Key Control Structures:
  • Conditional Branching:

    IF Tank_Level_PV >= High_High_Trip THEN
        Inlet_Valve_Cmd := FALSE;
        Dump_Valve_Cmd  := TRUE;
        Trip_Alarm_Active := TRUE;
    ELSIF Tank_Level_PV >= High_Warning THEN
        Inlet_Valve_Cmd := FALSE;
        Dump_Valve_Cmd  := FALSE;
    ELSE
        Inlet_Valve_Cmd := Auto_Fill_Permit;
        Dump_Valve_Cmd  := FALSE;
    END_IF;
    

  • Multi-Branch State Selection:

    CASE System_State OF
        0: (* System Idle *)
            Ready_Light := TRUE;
            Conveyor_Run := FALSE;
        1: (* Accelerating *)
            Conveyor_Run := TRUE;
            Speed_Cmd := Speed_Cmd + Acceleration_Rate;
        2: (* Steady State Run *)
            Speed_Cmd := Nominal_Speed;
        3: (* Decelerating / Fault *)
            Conveyor_Run := FALSE;
            Speed_Cmd := 0.0;
    ELSE
        System_State := 3;
    END_CASE;
    

  • Iterative Loops: FOR...TO...BY...DO, WHILE...DO, and REPEAT...UNTIL. Crucial rule: Loops must be strictly bounded. An infinite loop in a cyclic PLC task will trigger the hardware watchdog timer and fault the controller.
• Application Strengths: Complex trigonometric and thermodynamic calculations, array sorting, string manipulation for barcode scanners or serial printers, recipe file parsing, and algorithmic state machines.

4. Sequential Function Chart (SFC)

Sequential Function Chart is a graphical language designed to partition complex sequential, event-driven, and batch processes into distinct chronological stages. SFC is directly derived from Petri Nets and IEC 60848 (GRAFCET).

• Fundamental Building Blocks:
  1. Steps: Represent stable physical states of the process. An Initial Step ([[Initial_Step]]) is automatically active upon controller cold start. Subsequent steps ([Step_Name]) become active only when the preceding transition evaluates TRUE.
  2. Transitions: Boolean barrier conditions separating steps. A transition evaluates the process state. When the transition condition evaluates TRUE and its immediately preceding step is active, the preceding step deactivates and the successor step activates simultaneously.
  3. Actions: Control operations executed while a step is active. Actions are governed by Action Qualifiers:

• Divergence and Convergence Topologies:
  • Alternative Branching (OR-Divergence / OR-Convergence): Represented by a single horizontal line. Only one transition fires depending on mutually exclusive process conditions. Execution proceeds down exactly one branch.
  • Simultaneous Branching (AND-Divergence / AND-Convergence): Represented by a double horizontal line. When the preceding transition fires, all parallel branches activate concurrently. An AND-Convergence requires all parallel branches to reach their final steps before the succeeding transition can be evaluated.

SEQUENTIAL FUNCTION CHART (Simultaneous AND Branching):

                  [ Step 10: Reactor_Ready ]
                             |
                        [T1: Start_PB]
                             |
               ==============+==============  (AND-Divergence: Double Line)
               |                           |
      [ Step 20: Fill_Solvent ]   [ Step 30: Start_Agitator ]
               |                           |
      [T2: Level_High]            [T3: Speed_Confirmed]
               |                           |
               ==============+==============  (AND-Convergence: Double Line)
                             |
                      [T4: Temp_Stable]
                             |
                  [ Step 40: Heat_Mixture ]

5. Instruction List (IL): Deprecated, Then Removed

Instruction List is a low-level, text-based, accumulator-oriented language resembling assembly language. Instructions consist of operators (e.g., LD [Load], ST [Store], AND, OR, ADD, SUB, JMP [Jump]) operating on a single accumulator register.

INSTRUCTION LIST CODE SNIPPET (Motor Control):
LD      Start_PB
OR      Motor_Run
ANDN    Stop_PB
ANDN    Overload_Trip
ST      Motor_Run

Why IL Was Deprecated and Removed

The third edition of IEC 61131-3 (2013) formally deprecated Instruction List, and the fourth edition (May 2025) removed it from the standard, reflecting the view that an assembler-like language no longer fits modern development environments. The practical reasons include:

1. Lack of Type Safety: Low-level registers permit accidental bitwise operations on floating-point data, bypassing compiler type checking.
2. High Bug Density & Poor Readability: Accumulator-based instructions lack structured nesting, making large programs difficult to review, audit, and debug.
3. Compiler Optimization: Modern PAC 32-bit and 64-bit multi-core processors compile Structured Text directly to native machine code with higher execution efficiency than IL-interpreted stacks.
4. Superseded by Structured Text: Structured Text accommodates all algorithmic requirements with modern structured programming safeguards (IF-THEN, CASE, strong typing).

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Language Selection Guidelines

A Certified Automation Professional must not impose a single language across an entire project. Sound automation engineering mandates matching the programming language to the physical nature of the subsystem.

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Realistic Industrial Scenario: Polypropylene Extrusion Line

An automation engineering team is developing the control architecture for a twin-screw polypropylene pellet extrusion line. The system comprises four distinct functional domains:

1. Feed Throat Gravimetric Blenders: High-speed load cells continuously weigh and meter resin pellets and color masterbatch. Complex loss-in-weight differential equations calculate instantaneous mass flow rates ($dm/dt$) and dynamically update screw feeder drive setpoints every 20 ms.
   • Language Selected: Structured Text (ST). The differential calculus, floating-point filtering, and array averaging are expressed compactly without sprawling graphical blocks.
2. Extruder Barrel Temperature Zones: Twelve barrel heating/cooling zones require cascade PID loops with dynamic anti-windup, auto-tuning, and thermocouple lead/lag compensation.
   • Language Selected: Function Block Diagram (FBD). Visual representation of PID blocks, setpoint ramps, and split-range heating/cooling outputs allows process engineers to tune zones rapidly.
3. Line Sequencing & Pelletizer Startup: The line follows a strict startup procedure: Barrel Pre-Heat $\rightarrow$ Die Head Pressure Equalization $\rightarrow$ Screw Slow-Jog $\rightarrow$ Water Bath Fill $\rightarrow$ Strand Cutter Start $\rightarrow$ Full Production.
   • Language Selected: Sequential Function Chart (SFC). The step-transition topology prevents operators from accelerating the main drive before the die head reaches operating temperature.
4. Downstream Safety Guarding & Drive Interlocks: Emergency-stop pull cables, drive disconnect switches, lube oil pressure switches, and motor overload contacts.
   • Language Selected: Ladder Diagram (LD). Maintenance electricians require immediate visual rung diagnostics to isolate open field contacts during mechanical trips.

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Common Exam Traps

1. Treating Functions (FUN) and Function Blocks (FB) as Interchangeable: Exam items frequently ask which POU can house a timer, totalizer, or filter. Remember: Functions are stateless and have no instance memory; Function Blocks possess instance data blocks and retain static memory across scans.
2. Misinterpreting SFC Action Qualifier S (Set/Stored): A frequent trap assumes that an action qualified with S terminates when its step deactivates. It does not; a Set action continues executing indefinitely until another step executes a Reset (R) qualifier on that same action.
3. Selecting Graphical Languages for String or Array Operations: When an exam scenario describes parsing an ASCII telegram from a barcode reader or calculating a 50-point rolling statistical median, eliminate Ladder Diagram and Function Block Diagram. Structured Text is the only appropriate IEC 61131-3 language for string and array processing.