6.3 ARINC 664/AFDX and MIL-STD-1553 Avionics Architectures

6.3 ARINC 664/AFDX and MIL-STD-1553 Avionics Architectures

Quick Answer: Modern commercial airliners (Boeing 787, Airbus A380/A350) utilize ARINC 664 Part 7 (Avionics Full-Duplex Switched Ethernet / AFDX) to achieve deterministic $100\text{ Mbps}$ communication. AFDX replaces collision-prone shared Ethernet with dedicated logical Virtual Links (VLs) governed by a minimum transmit interval known as the Bandwidth Allocation Gap (BAG, $1$ to $128\text{ ms}$) and dual-redundant physical networks (Networks A & B) with First-Come, First-Served frame integrity checking. For military and special-mission aircraft, MIL-STD-1553B provides a dual-redundant, command/response $1.0\text{ Mbps}$ serial databus using Manchester II biphase encoding over $78\ \Omega$ shielded twisted pairs. In MIL-STD-1553B, a solitary Bus Controller (BC) directs all message traffic between up to 31 Remote Terminals (RTs), utilizing transformer-coupled stubs (up to 20 feet) with isolation resistors to prevent stub short circuits from disabling the main bus.

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ARINC 664 Part 7 / AFDX Principles

As civil transport aircraft evolved into integrated modular avionics (IMA) architectures, the bandwidth limitations and point-to-point wiring weight of ARINC 429 became prohibitive. Standard commercial off-the-shelf (COTS) IEEE 802.3 Ethernet offered abundant bandwidth ($100\text{ Mbps}$ to $1\text{ Gbps}$), but its native Media Access Control protocol was inherently unsuitable for flight-critical aviation:

• Non-Deterministic Latency: Standard half-duplex Ethernet uses CSMA/CD, which introduces random exponential backoff intervals upon collisions. Standard commercial full-duplex Ethernet switches experience unpredictable buffer queuing and packet drops during traffic bursts.
• Certification Barrier: Flight-critical data needs a bounded, provable worst-case latency and predictable delivery that certification authorities can verify.

To overcome this, Airbus developed and ARINC standardized ARINC 664 Part 7, commonly known as Avionics Full-Duplex Switched Ethernet (AFDX). AFDX bridges commercial Ethernet technology and aerospace deterministic safety by introducing deterministic Virtual Links (VL), hardware traffic shaping, and dual-network hardware redundancy.

+--------------------+            +--------------------+
|  End System (Tx)   |            |  End System (Rx)   |
|  Flight Control    |            |  Actuator Control  |
+----+----------+----+            +----+----------+----+
     |          |                      |          |
   Port A     Port B                 Port A     Port B
     |          |                      |          |
+----+----+   +-+-------+        +-----+---+   +--+------+
| Switch  |   | Switch  |        | Switch  |   | Switch  |
| Net A   |   | Net B   |========| Net A   |   | Net B   |
+---------+   +---------+        +---------+   +---------+

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Virtual Links (VL) and Bandwidth Allocation Gap (BAG)

In an AFDX network, communication is structured around the concept of a Virtual Link (VL), which represents a dedicated, unidirectional logical path from a single transmitting End System to one or more receiving End Systems across the switched network.

Virtual Link Identification

• Each VL is assigned an explicit 16-bit Virtual Link ID (VL-ID).
• This 16-bit identifier occupies the last two bytes of the 48-bit Ethernet destination MAC address, after a fixed 32-bit prefix that marks the address as a locally administered multicast address.
• AFDX switches use static routing tables to forward incoming frames strictly based on this VL-ID, eliminating dynamic MAC address learning and broadcast storms.

Bandwidth Allocation Gap (BAG)

To guarantee that no single transmitting End System can monopolize a switch or flood the network, every VL is configured with a strict Bandwidth Allocation Gap (BAG):

• BAG Definition: The minimum guaranteed time interval that must elapse between the transmission of consecutive Ethernet frames on that specific Virtual Link.
• Permitted Values: Under ARINC 664, BAG values are constrained strictly to powers of 2 in milliseconds: $\text{BAG} \in \{1, 2, 4, 8, 16, 32, 64, 128\}\ \text{ms}$

Maximum Frame Size and Bounded Bandwidth

Each VL is also allocated a Maximum Frame Length ($L_{\text{max}}$), ranging from 64 to 1518 bytes. By fixing both the BAG and $L_{\text{max}}$, the maximum allowable bandwidth for any Virtual Link is mathematically bounded:

$\text{Bandwidth}_{\text{VL}} = \frac{L_{\text{max}} \times 8}{\text{BAG}}$

Worked Scenario: An engine full-authority digital engine control (FADEC) End System transmits telemetry over a Virtual Link defined with $L_{\text{max}} = 1000\text{ bytes}$ and a $\text{BAG} = 8\text{ ms}$ ($0.008\text{ seconds}$):

$\text{Bandwidth} = \frac{1000\text{ bytes} \times 8\text{ bits/byte}}{0.008\text{ s}} = \frac{8000\text{ bits}}{0.008\text{ s}} = 1{,}000{,}000\text{ bps} = 1.0\text{ Mbps}$

Switch Hardware Traffic Policing and Max Jitter

Every port on an AFDX switch contains an active hardware traffic policer (token bucket algorithm). If an End System malfunctions and attempts to transmit frames faster than its allocated BAG (violating its bandwidth envelope), the switch immediately discards the violating frames at the ingress port. This guarantees that misbehaving LRUs cannot starve other flight-critical systems.

Because all VL paths, BAGs, and frame lengths are fixed, designers can compute the worst-case jitter and latency for every VL and prove bounded, deterministic delivery before certification.

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AFDX Dual-Redundant Physical Networks (Networks A and B)

To ensure complete fault tolerance against cable severing, connector backshell damage, or switch power loss, every AFDX installation deploys two completely independent, physically segregated networks: Network A and Network B.

Transmitting Host
       |
  [Duplicate Frame]
     /       \
 [Net A]   [Net B]  <-- Transmitted simultaneously on both physical cables
    |         |
  (Switch)  (Switch)
    |         |
     \       /
 [First-Come First-Served]
 [Sequence Number Check ]
       |
  Accepted Frame to Rx Host

Frame Duplication and Sequence Numbering

1. Simultaneous Transmission: When an onboard application dispatches a message, the transmitting End System's AFDX protocol stack duplicates the payload into two identical Ethernet frames. One frame is sent over Network A and the other over Network B simultaneously.
2. 1-Byte Sequence Number (SN): Immediately preceding the 4-byte Ethernet Frame Check Sequence (FCS), the End System appends a 1-byte Sequence Number (values 1 through 255, which increments with each new transmission and wraps from 255 back to 1; 0 is reserved for network reset/test).
3. First-Come, First-Served (FCFS) Frame Acceptance:
   • The receiving End System monitors both Network A and Network B ports.
   • Whichever frame arrives first with the expected sequence number is verified for integrity, accepted, and passed to the flight computer.
   • When the twin frame arrives on the other network (typically microseconds later), the receiver recognizes its duplicate sequence number and instantly discards it.
   • If Network A is severed, the frame on Network B delivers the data seamlessly without software intervention, zero failover delay, and zero dropped packets.

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MIL-STD-1553B Avionics Architecture

First published by the U.S. Department of Defense in 1973, revised as MIL-STD-1553B in 1978, and updated by Notice 2 in 1986, MIL-STD-1553B is the military and aerospace benchmark standard for digital command/response time-division multiplexed databuses. In service on combat aircraft (F-16, F/A-18, F-15), military transports (C-17, C-130J), attack helicopters (AH-64), and space missions (International Space Station), MIL-STD-1553B provides exceptional reliability under severe environmental and electromagnetic conditions.

Foundational Architecture

• Topology: Dual-redundant serial linear transmission bus (designated Bus A and Bus B). Both buses run in parallel throughout the airframe.
• Data Rate: 1.0 Mbps ($1.0\ \mu\text{s}$ per bit cell).
• Modulation: Manchester II Biphase-Level Coding.
• Transmission Media: Shielded twisted pair with a characteristic impedance ($Z_0$) of $70\ \Omega$ to $85\ \Omega$ (nominal $78\ \Omega$).
• Bus Termination: Both ends of the main trunk line are terminated with a resistor equal to the cable's nominal characteristic impedance ($78\ \Omega \pm 2\%$, 2W).

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Manchester II Biphase-Level Coding

Unlike NRZ signaling where a voltage level remains steady across a bit time, MIL-STD-1553B uses Manchester II biphase-level encoding:

• Every bit cell has a duration of exactly $1.0\ \mu\text{s}$.
• Mid-Bit Transition: An electrical transition always occurs at the center ($0.5\ \mu\text{s}$) of the bit cell.
• Logic HIGH ('1'): The signal begins as a positive voltage ($+V$) for the first $0.5\ \mu\text{s}$, then transitions to a negative voltage ($-V$) for the second $0.5\ \mu\text{s}$.
• Logic LOW ('0'): The signal begins as a negative voltage ($-V$) for the first $0.5\ \mu\text{s}$, then transitions to a positive voltage ($+V$) for the second $0.5\ \mu\text{s}$.

Voltage (V)
  +V  |    +----+              +----+
      |    |    |              |    |
   0V |----+----+----+----+----+----+----+----
      |         |    |    |         |    |
  -V  |         +----+    +----+    +----+
      +---------------------------------------
      |<-- Logic 1 -->| <-- Logic 0 -->|
      | +0.5us | -0.5us| -0.5us | +0.5us|

Engineering Advantages of Manchester II

1. Inherent Self-Clocking: Because an electrical transition occurs during every single bit cell, receiving decoders synchronize their clocks to the mid-bit edge, eliminating separate clock cabling.
2. Zero DC Component: Because every bit consists of equal durations of positive and negative voltage, the net DC voltage average across any word is mathematically zero. This allows the bus to pass through isolation transformers without saturating magnetic cores.
3. Unique Hardware Sync Pulses: Words begin with a unique 3-bit-wide sync pattern that violates normal Manchester coding (1.5 bit times at $+V$ followed by 1.5 bit times at $-V$). This allows decoders to synchronize instantly to word boundaries.

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MIL-STD-1553B Terminal Types

A MIL-STD-1553B databus operates under strict centralized master-slave control. There are exactly three functional device categories:

1. Bus Controller (BC):
   • The sole master device on the databus.
   • Initiates all data transfers, issues command words, schedules periodic messages, and receives status replies.
   • Strict Rule: Only ONE active Bus Controller exists at any given instant. A backup Bus Controller can take over only via an explicit dynamic bus control handover command.
2. Remote Terminal (RT):
   • Slave LRUs that interface sensors, weapons, displays, and actuators to the bus.
   • Can never initiate communication autonomously; an RT transmits data only when commanded by the BC.
   • Addressing: Up to 31 discrete RT addresses (assigned 0 through 30 via connector address pins; address 31 is standardly reserved for global Broadcast commands).
3. Bus Monitor (BM):
   • A passive, listen-only terminal that captures and records bus traffic for flight data recorders (FDR) or maintenance diagnostic laptops.
   • A Bus Monitor never transmits or acknowledges messages on the bus, ensuring it cannot interfere with active command/response transactions.

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Stub Coupling Methods: Transformer-Coupled vs. Direct-Coupled

When connecting an LRU to the main MIL-STD-1553B databus trunk, technicians utilize either transformer coupling or direct coupling.

Transformer-Coupled Stub (Long Stub):    Direct-Coupled Stub (Short Stub):
Main Bus Trunk                          Main Bus Trunk
====+=====================+====         ====+=====================+====
    |  Coupler Box        |                 | (Splice)
   [R] Isolation Resistors|                 | No Coupler Box
   [R] (0.75 * Z_0)       |                 | (Max Stub Length = 1.0 ft)
    |                     |                 |
   (T) Isolation Xfmr     |                 |
    |  (1.41:1 Turns)     |                 |
    +----------+----------+                 |
               |                            |
               | Cable <= 20 ft             | Cable <= 1 ft
               v                            v
          To LRU (RT)                  To LRU (RT)

1. Transformer-Coupled Stubs (Recommended Aerospace Standard)

• Architecture: The main bus connects to an external data bus coupler box containing an isolation transformer ($1.41:1$ turns ratio) and two internal fault isolation resistors ($R_{\text{iso}} = 0.75 \times Z_0$, about 56 to 59 Ω for 75 to 78 Ω cable).
• Short-Circuit Protection: If an LRU stub cable is severed, crushed, or internally short-circuited, the isolation resistors and transformer isolate the fault, preventing the short from collapsing the main bus trunk.
• Maximum Stub Length: Allows stub cable runs up to 20.0 feet (6.1 meters) from the main trunk to the LRU.
• Signal Amplitude: A transformer-coupled terminal's transmitter must produce 18.0 to 27.0 V peak-to-peak (line to line) on its stub, while a direct-coupled terminal produces 6.0 to 9.0 V peak-to-peak.

2. Direct-Coupled Stubs

• Architecture: The stub cable splices directly into the main bus trunk without an external transformer coupler box. Isolation resistors of about $55\ \Omega$ are located inside the terminal.
• Vulnerability: A short circuit on the stub cable before the LRU can reflect zero impedance directly onto the main bus, taking down communication for all terminals.
• Maximum Stub Length: Strictly restricted to a maximum length of 1.0 foot (0.3 meters) to prevent severe capacitive loading and transmission line reflections.