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Key Facts: EGEL Plus Ingeniería Computacional Exam

200

Total items on the official EGEL Plus ICOMPU (140 disciplinary + 60 transversal)

Ceneval, Guía para el sustentante EGEL Plus ICOMPU

9 hours

Two sessions of 4.5 hours each on the same day

Ceneval, Guía para el sustentante EGEL Plus ICOMPU

1000

Minimum Índice Ceneval for a Satisfactorio level in an area or section

Ceneval, Guía para el sustentante EGEL Plus ICOMPU

1150

Minimum Índice Ceneval for a Sobresaliente level

Ceneval, Guía para el sustentante EGEL Plus ICOMPU

MXN 1,885

Individual national Examen desde casa fee in 2026

Ceneval EGEL portal

Ceneval's EGEL Plus ICOMPU is a 200-item, nine-hour Spanish exit exam: 140 disciplinary items in three areas plus 60 transversal language and communication items.

Sample EGEL Plus Ingeniería Computacional Practice Questions

Try these sample questions to review concepts for the EGEL Plus Ingeniería Computacional exam. Each question includes a detailed explanation. Start the interactive quiz above for the full 100+ question experience with AI tutoring.

1A microprocessor memory subsystem has an L1 cache hit time of 1 ns with an L1 miss rate of 5%. The L2 cache has a hit time of 4 ns with a local miss rate of 20%. The main memory access penalty is 50 ns. What is the Average Memory Access Time (AMAT) of this system?
A.1.70 ns
B.3.70 ns
C.1.20 ns
D.11.20 ns
Explanation: AMAT is calculated as Hit_Time_L1 + (Miss_Rate_L1 × Miss_Penalty_L1). The L1 miss penalty is the L2 access time plus the penalty of missing in L2: Miss_Penalty_L1 = Hit_Time_L2 + (Miss_Rate_L2 × Miss_Penalty_L2) = 4 ns + (0.20 × 50 ns) = 4 ns + 10 ns = 14 ns. Substituting this back yields AMAT = 1 ns + (0.05 × 14 ns) = 1 ns + 0.70 ns = 1.70 ns.
2A system uses 32-bit byte-addressed physical memory and a 256 KB 8-way set-associative cache with 64-byte blocks. How are the 32 address bits divided into Tag, Index, and Block Offset fields?
A.Tag: 17 bits, Index: 9 bits, Offset: 6 bits
B.Tag: 14 bits, Index: 12 bits, Offset: 6 bits
C.Tag: 16 bits, Index: 10 bits, Offset: 6 bits
D.Tag: 18 bits, Index: 8 bits, Offset: 6 bits
Explanation: With 64-byte blocks, the block offset needs log2(64) = 6 bits. The cache holds 256 KB = 262,144 bytes, so it has 262,144 / 64 = 4,096 lines. With 8 ways, there are 4,096 / 8 = 512 sets, which need log2(512) = 9 index bits. The tag takes the remaining 32 − (9 + 6) = 17 bits.
3A synchronous digital pipeline stage consists of edge-triggered D flip-flops with clock-to-Q delay t_cq = 0.8 ns, setup time t_setup = 1.0 ns, and hold time t_hold = 0.5 ns. The critical combinational logic path delay between flip-flops is 6.2 ns with a clock skew of 0.0 ns. What is the theoretical maximum clock frequency (f_max) for reliable operation?
A.125.0 MHz
B.142.9 MHz
C.161.3 MHz
D.117.6 MHz
Explanation: The minimum clock period T_min is determined by the setup constraint: T_min ≥ t_cq + t_comb_max + t_setup. Substituting the values gives T_min = 0.8 ns + 6.2 ns + 1.0 ns = 8.0 ns. The maximum operating frequency is f_max = 1 / T_min = 1 / (8.0 × 10⁻⁹ s) = 125 × 10⁶ Hz = 125.0 MHz.
4An embedded microcontroller operates with a system clock of 16 MHz. An engineer configures an internal 16-bit up-counting timer with a prescaler of 8 to generate a periodic PWM carrier frequency of exactly 1.0 kHz in fast PWM mode (counting from 0 to TOP). What value must be loaded into the TOP register?
A.1999
B.2000
C.15999
D.999
Explanation: The timer input clock frequency is f_timer = f_clk / prescaler = 16 MHz / 8 = 2 MHz (period of 0.5 µs per tick). For a target PWM frequency of 1 kHz, the total period must be T_pwm = 1 / 1000 Hz = 1 ms = 1000 µs. The number of timer ticks per period is N = 1000 µs / 0.5 µs = 2000 ticks. Because the counter begins counting at 0 and wraps back after reaching TOP, the total count states are TOP + 1 = 2000, so TOP = 1999.
5A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) uses an analog reference voltage of Vref = 3.30 V with an input range from 0 V to Vref. What is the ideal quantization step size (voltage resolution of 1 LSB) of this converter?
A.3.22 mV
B.6.45 mV
C.1.61 mV
D.0.32 mV
Explanation: A 10-bit ADC provides 2¹⁰ = 1,024 discrete quantization levels. The quantization step size (1 LSB voltage) is defined as Q = Vref / 2ⁿ = 3.30 V / 1024 = 0.0032226 V ≈ 3.22 mV (or 3.30 V / 1023 ≈ 3.23 mV for code transitions).
6Which minimal sum-of-products (SOP) boolean expression represents the output F(A,B,C,D) defined by minterms Σm(0, 2, 8, 10) in a 4-variable Karnaugh map?
A.B' D'
B.A' C'
C.B' C
D.A D'
Explanation: Minterms m0 (0000), m2 (0010), m8 (1000), and m10 (1010) occupy the four corner cells of a 4-variable Karnaugh map. In these four cells: A changes (0 in m0, m2; 1 in m8, m10), B remains 0 (B'), C changes (0 in m0, m8; 1 in m2, m10), and D remains 0 (D'). Grouping the four corner cells eliminates variables A and C, yielding the minimal product term B' D'.
7In synchronous sequential circuit design, which condition MUST hold to prevent a hold time violation at the destination flip-flop?
A.t_cq_min + t_comb_min ≥ t_hold + t_skew
B.t_cq_max + t_comb_max + t_setup ≤ T_clock
C.t_comb_max ≥ t_cq_max + t_setup
D.t_skew ≥ t_hold - t_cq_min
Explanation: A hold time violation occurs if newly launched data arrives at the destination flip-flop before the destination flip-flop has reliably latched the previous data value. The shortest possible propagation delay from the launching clock edge to the destination input (t_cq_min + t_comb_min) must be greater than or equal to the required hold time plus any positive clock skew (t_hold + t_skew).
8What phenomenon occurs in an unclocked or level-sensitive JK latch when both inputs J and K are held HIGH (J = 1, K = 1) while the enable/clock pulse remains active longer than the propagation delay of the gates?
A.Race-around condition causing uncontrollable toggling of the output
B.Metastability causing the output voltage to lock at the midpoint logic threshold
C.Permanent gate burnout due to internal bus contention
D.Immediate latch reset to Q = 0 regardless of prior state
Explanation: When J = 1 and K = 1 in a level-sensitive latch, the output toggles (Q becomes Q'). If the clock pulse width t_p is greater than the internal gate propagation delay t_pd, the newly toggled output feeds back to the inputs while the clock is still HIGH, causing the output to toggle repeatedly and unpredictably throughout the pulse duration. This is called the race-around condition, resolved by using master-slave latches or edge-triggered flip-flops.
9What is the primary architectural difference between a Moore finite state machine (FSM) and a Mealy finite state machine?
A.Moore outputs depend solely on the current state, whereas Mealy outputs depend on both current state and primary inputs
B.Moore machines require fewer states than Mealy machines to implement any arbitrary sequential sequence
C.Mealy machines update state registers asynchronously, whereas Moore machines require a synchronous system clock
D.Moore machines evaluate outputs purely during clock transitions, whereas Mealy machines cannot use clock signals
Explanation: In a Moore machine, the output logic is a function of the current state register bits only: Output = λ(State). In a Mealy machine, the outputs are combinational functions of both the current state and the current external inputs: Output = λ(State, Inputs). As a consequence, Mealy outputs can react within the current clock cycle to input changes, whereas Moore outputs only change upon state transitions on clock edges.
10An 8-to-1 digital multiplexer has three selection lines S2, S1, S0 connected to inputs A, B, and C respectively. To implement the boolean function F(A, B, C, D) = A'B'C'D + A'BC'D' + ABC, what signals must be applied to data inputs I0 through I7?
A.I0 = D, I2 = D', I7 = 1, with all other inputs tied to 0
B.I0 = D, I2 = D', I6 = 1, I7 = 1, with all other inputs tied to 0
C.I1 = D, I3 = D', I7 = 1, with all other inputs tied to 0
D.I0 = D', I2 = D, I7 = 1, with all other inputs tied to 0
Explanation: With S2 S1 S0 = A B C, each data input Ik equals F for that combination of A, B, C expressed as a function of D. ABC = 000 (I0): only A'B'C'D applies, so I0 = D. ABC = 010 (I2): only A'BC'D' applies, so I2 = D'. ABC = 111 (I7): the term ABC is true for either value of D, so I7 = 1. No term covers 001, 011, 100, 101, or 110, so I1, I3, I4, I5, and I6 are tied to 0.

About the EGEL Plus Ingeniería Computacional Exam

Independent EGEL Plus Ingeniería Computacional practice by OpenExamPrep. The official Ceneval examination is in Spanish and has 200 three-option items: 140 disciplinary items in Implementación de hardware, Implementación de redes de computadoras, and Desarrollo de software, and 60 transversal Lenguaje y Comunicación items. This bank is an English-language study adaptation with four-option multiple-choice questions, not an official translation or format simulation. Disciplinary stems and explanations are in English. Language and communication items keep their Spanish passages and answer options, because Spanish usage is the skill being tested, and give their instructions and explanations in English.

Exam sponsor: Centro Nacional de Evaluación para la Educación Superior (Ceneval). The requirements and fees below concern the certification or admission exam, separate from our free practice resources.

Assessment

200 three-option items: 140 disciplinary items (Implementación de hardware 49, Implementación de redes de computadoras 41, Desarrollo de software 50) and 60 transversal items in Comprensión Lectora and Redacción Indirecta.

Time Limit

Two sessions of 4.5 hours each on the same day (9 hours in total)

Passing Score

Each area and each section is reported on the Índice Ceneval (700-1300): 700-999 Aún no satisfactorio, 1000-1149 Satisfactorio, 1150-1300 Sobresaliente. The global result is weighted toward the disciplinary section: Satisfactorio or better there earns at least a Testimonio de Desempeño Satisfactorio, and a Testimonio de Desempeño Sobresaliente requires Sobresaliente in the disciplinary section and at least Satisfactorio in Lenguaje y Comunicación

Exam / Certification Fees

MXN 1,885 for the 2026 national Examen desde casa; institutional administrations may charge a different amount

Exam sponsor website

Fees, eligibility, and exam policies can change. Confirm them with the exam sponsor before applying or paying.

Official sources

Our practice resources: topics covered

We aim to reflect publicly available exam outlines and topic information in our study resources. Coverage, format, and difficulty may differ from the actual exam, and we cannot guarantee that every detail is accurate or current. Confirm exam requirements, fees, and policies with the official exam sponsor.

49 of 140 disciplinary items

Implementación de hardware

Electric circuits and electronics (11), computer architecture and organization (11), embedded systems (13), and process automation and control (14)

41 of 140 disciplinary items

Implementación de redes de computadoras

Network design (11), network administration (13), and network security and evaluation (17)

50 of 140 disciplinary items

Desarrollo de software

Software engineering (16), programming and system software (13), and data handling and algorithms (21)

60 of 200 total items

Lenguaje y Comunicación

Reading comprehension of academic, literary and public-interest texts (30 items) and indirect writing, which asks candidates to choose the version of a text that is correct, coherent and well punctuated (30 items)

Preparing for the EGEL Plus Ingeniería Computacional Exam

What You Need to Know

  • Passing score: Each area and each section is reported on the Índice Ceneval (700-1300): 700-999 Aún no satisfactorio, 1000-1149 Satisfactorio, 1150-1300 Sobresaliente. The global result is weighted toward the disciplinary section: Satisfactorio or better there earns at least a Testimonio de Desempeño Satisfactorio, and a Testimonio de Desempeño Sobresaliente requires Sobresaliente in the disciplinary section and at least Satisfactorio in Lenguaje y Comunicación
  • Assessment: 200 three-option items: 140 disciplinary items (Implementación de hardware 49, Implementación de redes de computadoras 41, Desarrollo de software 50) and 60 transversal items in Comprensión Lectora and Redacción Indirecta.
  • Time limit: Two sessions of 4.5 hours each on the same day (9 hours in total)
  • Exam / certification fees: MXN 1,885 for the 2026 national Examen desde casa; institutional administrations may charge a different amount Official sources

Using Our Practice Resources

  • Work through all 100 available questions
  • Review every answer and explanation
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EGEL Plus Ingeniería Computacional: Suggested Study Strategy

1Practice hardware calculations: Thévenin equivalents, RC transients, 4-20 mA scaling, cache address fields, AMAT, and pipeline hazards.
2Review embedded systems: timer and PWM settings, ADC resolution, interrupts, DMA, and SPI, I2C and UART framing.
3Drill networking: VLSM subnetting, bandwidth-delay product, switching and STP, OSPF and BGP behavior, and firewall, IPsec and TLS basics.
4Data handling and algorithms is the largest subarea (21 items): review complexity, trees, hashing, graph algorithms, normalization and SQL.
5Prepare for Lenguaje y Comunicación by reading academic articles, essays and public notices in Spanish, and by reviewing agreement, punctuation, accentuation and connectors.

Frequently Asked Questions

What is the EGEL Plus Ingeniería Computacional?

The EGEL Plus Ingeniería Computacional (EGEL Plus ICOMPU) is Ceneval's national exit examination for graduates of the Licenciatura en Ingeniería Computacional and related programs. It measures the knowledge and skills considered indispensable at the end of the degree, plus Spanish reading comprehension and indirect writing. Institutions may use the result as a graduation requirement, a titulación option or part of a course grade, under their own rules; a Testimonio does not by itself determine the award of the degree or the cédula profesional.

How many questions are on the official EGEL Plus ICOMPU and how long is it?

The official exam has 200 items: 140 disciplinary items (Implementación de hardware 49, Implementación de redes de computadoras 41, Desarrollo de software 50) and 60 Lenguaje y Comunicación items (30 reading comprehension and 30 indirect writing). It is given on one day in two sessions of 4.5 hours each (9 hours). About 15% of the items are pilot items that do not count toward the result.

How is the EGEL Plus ICOMPU scored?

Each area and section is reported on the Índice Ceneval from 700 to 1300: 700-999 Aún no satisfactorio, 1000-1149 Satisfactorio and 1150-1300 Sobresaliente. The global result follows a conjunctive rule weighted toward the disciplinary section: Satisfactorio or better in the disciplinary section earns at least a Testimonio de Desempeño Satisfactorio, while a Testimonio de Desempeño Sobresaliente requires Sobresaliente in the disciplinary section and at least Satisfactorio in Lenguaje y Comunicación. Candidates with a global Sobresaliente who take the exam for the first time within one year of finishing the degree are eligible for the Premio Ceneval al Desempeño de Excelencia-EGEL.

Can I use a calculator or formula sheet on the EGEL Plus ICOMPU?

Yes. The official guide allows a non-programmable scientific calculator, which may not be shared between candidates. No formula sheet is listed among the permitted materials, so memorize the formulas you need.

Why is this practice bank in English if the official exam is in Spanish?

The official Ceneval exam is in Spanish. This bank is an independent English-language study adaptation with four-option questions, not an official translation or format simulation. Disciplinary questions and explanations are in English so you can review the engineering content. Language and communication items keep their Spanish passages and options because they test Spanish usage, and their instructions and explanations are in English.

How does EGEL Plus Ingeniería Computacional differ from EGEL Plus Ingeniería de Software?

They are separate Ceneval exams. Ingeniería Computacional gives hardware implementation (49 items) and computer networks (41 items) nearly as much weight as software development (50 items), so circuits, computer architecture, embedded systems and automation are a major part of the preparation.