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Exam Review

Key Facts: GCE A/L Information & Communication Technology Exam

50

Official Paper 1 MCQs

DoENETS Sri Lanka

2 Hours

Paper 1 Duration

DoENETS Sri Lanka

3 Hours

Paper 2 Duration

DoENETS Sri Lanka

35 Marks

Minimum Pass (S Grade)

DoENETS Standard

100

Practice Bank Items

OpenExamPrep

Sri Lanka GCE A/L ICT (Subject Code 20) assesses students through Paper 1 (50 MCQs, 2 hours) and Paper 2 (structured & essay, 3 hours). The exam covers hardware, digital logic, networking, databases, Python programming, systems analysis, and web technologies. School candidates sit for free. This independent 100-question practice bank delivers comprehensive coverage and detailed explanations for Paper 1 preparation.

Sample GCE A/L Information & Communication Technology Practice Questions

Try these sample questions to review concepts for the GCE A/L Information & Communication Technology exam. Each question includes a detailed explanation. Start the interactive quiz above for the full 100+ question experience with AI tutoring.

1Which fundamental principle of the Von Neumann computer architecture distinguishes it from earlier computing machinery?
A.Data and program instructions are stored together in the same read-write memory address space.
B.Programs are hardwired into physical circuit patchboards and switches.
C.Arithmetic operations are executed entirely using mechanical gears and punch cards.
D.Separate physical memory units and distinct buses are used for instructions and data.
Explanation: The core concept of the Von Neumann architecture is the stored-program concept, where program instructions and data share a common read-write primary memory. Earlier calculating machines required physical rewiring or manual switch setting to change tasks. Sharing memory allows computers to dynamically load, modify, and execute programs without altering physical hardware.
2In the central processing unit (CPU), which register holds the memory address of the next instruction to be fetched from main memory?
A.Instruction Register (IR)
B.Program Counter (PC)
C.Memory Data Register (MDR)
D.Accumulator (ACC)
Explanation: The Program Counter (PC) stores the address of the subsequent instruction scheduled for execution. During the fetch stage of the machine cycle, the address in the PC is copied to the Memory Address Register (MAR), and the PC is automatically incremented to point to the next instruction in memory sequence.
3Which of the following correctly lists computer storage devices in order of increasing data access speed (from slowest to fastest)?
A.CPU Registers -> Cache Memory -> RAM -> Solid State Drive
B.Hard Disk Drive -> RAM -> Cache Memory -> CPU Registers
C.RAM -> Hard Disk Drive -> CPU Registers -> Cache Memory
D.Cache Memory -> RAM -> CPU Registers -> Magnetic Tape
Explanation: In the memory hierarchy, secondary magnetic storage like hard disk drives is the slowest due to mechanical seek times. Primary RAM is faster, followed by SRAM-based cache memory located near or inside the CPU core. CPU registers reside directly on the processor silicon and provide the fastest single-cycle access speeds.
4During the fetch phase of the CPU machine cycle, what is the precise sequence of micro-operations that transfers an instruction from RAM into the CPU?
A.PC -> IR -> Control Bus -> RAM -> MDR -> MAR; PC is decremented
B.MDR -> PC -> MAR -> ALU -> ACC -> IR; PC is cleared
C.PC -> MAR -> Address Bus -> RAM -> Data Bus -> MDR -> IR; PC is incremented
D.MAR -> PC -> Data Bus -> RAM -> Address Bus -> MDR -> IR; PC is doubled
Explanation: The fetch cycle starts when the address in the Program Counter (PC) is loaded into the Memory Address Register (MAR). The MAR places this address onto the address bus while the control unit signals a memory read. Memory returns the instruction byte over the data bus into the Memory Data Register (MDR), from where it is transferred to the Instruction Register (IR), and the PC is incremented.
5Which principle of program execution justifies the design and effectiveness of multi-level CPU cache memory?
A.Amdahl's law of diminishing returns in parallel computing pipelines
B.Von Neumann bottleneck constraint regarding shared memory buses
C.Moore's law governing the physical density of planar transistors
D.Locality of reference, comprising both temporal locality and spatial locality
Explanation: Cache effectiveness relies on the principle of locality of reference. Temporal locality states that memory locations accessed recently are likely to be accessed again soon (such as loop counters), while spatial locality states that memory locations adjacent to recently accessed addresses are likely to be accessed soon (such as sequential instructions and array elements).
6If a processor architecture utilizes a 32-bit address bus where each unique memory address designates exactly one byte, what is the maximum theoretical physical memory capacity it can directly address?
A.1 MiB (1,048,576 bytes)
B.2 GiB (2,147,483,648 bytes)
C.4 GiB (4,294,967,296 bytes)
D.64 GiB (68,719,476,736 bytes)
Explanation: An address bus with n lines can generate 2^n distinct binary addresses. For n = 32 lines with byte addressability, the CPU can reference 2^32 bytes = 4,294,967,296 bytes = 4 GiB of physical memory. Addressing beyond 4 GiB requires extending the address bus width, such as to 36 bits with PAE or using a 64-bit architecture.
7Which input/output transfer mechanism allows high-speed peripheral devices to transfer blocks of data directly to or from main memory without continuous CPU intervention?
A.Direct Memory Access (DMA)
B.Programmed I/O (Polling)
C.Interrupt-Driven I/O without controller
D.Software polling via accumulator
Explanation: Direct Memory Access (DMA) delegates block data transfers between high-speed peripheral controllers (such as disk controllers or network cards) and system RAM to a specialized DMA controller. Once initiated by the CPU, the DMA controller manages the bus transfers autonomously, freeing the CPU to execute other tasks and generating a single interrupt only upon block completion.
8Which of the following correctly matches computer generations with their primary enabling electronic switching technologies?
A.1st: Transistors; 2nd: Vacuum tubes; 3rd: Microprocessors; 4th: Magnetic drums
B.1st: Vacuum tubes; 2nd: Transistors; 3rd: Integrated circuits; 4th: Microprocessors (VLSI)
C.1st: Integrated circuits; 2nd: Thermionic valves; 3rd: Microchips; 4th: Relays
D.1st: Punch cards; 2nd: Delay lines; 3rd: Optical lasers; 4th: Quantum gates
Explanation: First-generation computers (1940s-1950s) utilized thermionic vacuum tubes. Second-generation machines (late 1950s-1960s) adopted discrete semiconductor transistors. Third-generation systems (mid-1960s-1970s) incorporated small/medium scale integrated circuits (ICs), and fourth-generation computers (1970s-present) are powered by Very Large Scale Integration (VLSI) microprocessors.
9A computer system features a cache memory with an access time of 2 nanoseconds (ns) and a main memory access time of 40 ns. If the cache hit ratio is 0.90 (90%), what is the Effective Memory Access Time (EMAT) assuming the cache and main memory are accessed hierarchically?
A.4.2 ns
B.5.8 ns
C.6.0 ns
D.38.0 ns
Explanation: Under hierarchical (sequential) access the cache is probed first and, only on a miss, main memory is then accessed, so the 2 ns cache probe is paid on every reference: EMAT = h x Tc + (1 - h) x (Tc + Tm) = Tc + (1 - h) x Tm = 2 + 0.10 x 40 = 2 + 4 = 6.0 ns. Had the two levels instead been accessed simultaneously, the result would be 0.90 x 2 + 0.10 x 40 = 5.8 ns.
10In instruction pipelining, which type of hazard occurs when an instruction depends on the result of an earlier instruction that has not yet completed its write-back stage?
A.Structural hazard (Resource contention)
B.Control hazard (Branch penalty)
C.Data hazard (Read-After-Write)
D.Dynamic interrupt hazard
Explanation: A data hazard arises when instructions that are close in the pipeline execution stream exhibit data dependencies, such as Read-After-Write (RAW). When instruction B requires the operand produced by instruction A before instruction A has committed its result to the register file, the pipeline must stall or use operand forwarding to avoid reading stale data.

About the GCE A/L Information & Communication Technology Exam

G.C.E. Advanced Level Information & Communication Technology (Subject Code 20) is a premier national secondary school qualification administered by the Department of Examinations, Sri Lanka under the Ministry of Education. Offered across Physical Science, Commerce, Arts, and Technology streams, the syllabus spans computer architecture, logic gates, digital systems, networking, databases, programming in Python, web development, and systems engineering. This independent practice bank provides 100 high-yield multiple-choice questions with step-by-step rationales to help students master core theoretical and practical problem-solving concepts for Paper 1.

Exam sponsor: Department of Examinations, Sri Lanka (doenets.lk). The requirements and fees below concern the certification or admission exam, separate from our free practice resources.

Assessment

Paper 1 contains 50 compulsory multiple-choice questions (2 hours, 100 marks weighted to 33.3% or 50% depending on the evaluation scheme). Paper 2 contains Section A (4 compulsory structured questions) and Section B (4 essay/programming questions selected from 6 options) over 3 hours.

Time Limit

Paper 1: 2 hours; Paper 2: 3 hours (Total 5 hours)

Passing Score

Grade S or higher

Exam / Certification Fees

Free for school candidates; nominal fee for private candidates

Exam sponsor website

Reported exam pass rate: Published annually in DoENETS national evaluation reports. University admission into state universities for ICT and computing degrees is determined competitively by national Z-score ranking. Exam sponsor website

Fees, eligibility, and exam policies can change. Confirm them with the exam sponsor before applying or paying.

Our practice resources: topics covered

We aim to reflect publicly available exam outlines and topic information in our study resources. Coverage, format, and difficulty may differ from the actual exam, and we cannot guarantee that every detail is accurate or current. Confirm exam requirements, fees, and policies with the official exam sponsor.

10%

Basic Concepts & Hardware Architecture

Evolution of computing devices, Von Neumann architecture, CPU components (ALU, CU, registers), cache memory, memory hierarchy, bus architecture, and I/O interfaces.

15%

Data Representation & Digital Logic

Binary, octal, hexadecimal, BCD, two's complement arithmetic, Boolean algebra laws, truth tables, Karnaugh maps (K-maps), basic and universal logic gates, and combinational circuits.

20%

Operating Systems & Networking

OS process scheduling, memory management, virtual memory, paging, file systems, OSI 7-layer and TCP/IP 4-layer models, network devices, IPv4 subnetting, IPv6, and network security.

15%

Database Management Systems & SQL

Relational data model, entity-relationship diagrams (ERD), normalization up to 3NF, SQL DDL and DML commands, aggregate queries, table joins, and ACID transaction properties.

10%

Systems Analysis, Design & Software Engineering

Software development life cycle (SDLC) models, requirements gathering techniques, context diagrams, Data Flow Diagrams (DFDs), deployment methods, and testing strategies.

15%

Programming & Algorithms

Algorithm development using flowcharts and pseudocode, Python programming syntax, control structures, functions, lists, dictionaries, file I/O, recursion, and standard sorting/searching algorithms.

15%

Web Technologies & Emerging Trends

HTML5 semantic markup, CSS3 styling and box model, client-side JavaScript DOM manipulation, server-side PHP scripting, cloud computing, Internet of Things (IoT), and AI fundamentals.

Preparing for the GCE A/L Information & Communication Technology Exam

What You Need to Know

  • Passing score: Grade S or higher
  • Assessment: Paper 1 contains 50 compulsory multiple-choice questions (2 hours, 100 marks weighted to 33.3% or 50% depending on the evaluation scheme). Paper 2 contains Section A (4 compulsory structured questions) and Section B (4 essay/programming questions selected from 6 options) over 3 hours.
  • Time limit: Paper 1: 2 hours; Paper 2: 3 hours (Total 5 hours)
  • Exam / certification fees: Free for school candidates; nominal fee for private candidates Official sources

Using Our Practice Resources

  • Work through all 100 available questions
  • Review every answer and explanation
  • Track weak areas and revisit them
  • Use our AI tutor for tough concepts

GCE A/L Information & Communication Technology: Suggested Study Strategy

1Master number conversions and binary arithmetic early: practice converting between decimal, binary, octal, and hexadecimal, and understand two's complement negative number representations and overflow.
2Work through Karnaugh maps methodically by grouping 1s in powers of two (1, 2, 4, 8) and checking wrap-around edges to ensure minimal Boolean expressions.
3Practice IPv4 subnetting calculations until you can rapidly identify network addresses, broadcast addresses, subnet masks, and usable host ranges from CIDR prefix notations like /26 or /28.
4Trace Python code line by line with a written trace table: keep columns for loop variables, conditional flags, list contents, and accumulator variables.
5Review relational database normalization rules step by step: eliminate repeating groups for 1NF, remove partial functional dependencies for 2NF, and eliminate transitive dependencies for 3NF.
6Pay close attention to HTML semantic elements, CSS specificity, HTTP request-response flow, and the distinction between client-side JavaScript and server-side PHP processing.

Frequently Asked Questions

What is the structure of the Sri Lanka GCE A/L ICT examination?

The examination comprises two written papers: Paper 1 consists of 50 compulsory multiple-choice questions (MCQs) administered over 2 hours. Paper 2 is a 3-hour paper divided into Section A (4 compulsory structured questions) and Section B (4 essay or problem-solving questions selected from 6 options, covering programming, database design, networking, and systems analysis).

Which programming language is officially assessed in GCE A/L ICT?

Python 3 is the official programming language assessed in the G.C.E. Advanced Level ICT curriculum, having replaced Pascal. Students are expected to read, trace, and write Python code including loops, conditional statements, user-defined functions, lists, dictionaries, string manipulations, and basic file operations.

What is the passing score and grading scheme for GCE A/L ICT in Sri Lanka?

Performance is reported using letter grades: A (75-100, Distinction), B (65-74, Very Good Pass), C (50-64, Credit Pass), S (35-49, Ordinary Pass), and F (0-34, Fail). A minimum grade of S in three subjects is required for general eligibility for higher education, while university degree program admission is based on the standardized Z-score.

In which languages can candidates sit for the GCE A/L ICT exam?

The examination is officially offered in all three national education media of Sri Lanka: Sinhala, Tamil, and English. Candidates can choose their medium of assessment when registering through their school or as private candidates.

How should I allocate time during the 50-question MCQ Paper 1?

Paper 1 provides 120 minutes for 50 questions, which allows an average of 2.4 minutes per question. It is recommended to answer straightforward theoretical questions (such as definitions, hardware terms, and protocol names) in under 1 minute each, preserving extra time for multi-step subnetting calculations, Karnaugh map simplifications, and Python trace tables.

How does this practice bank help with GCE A/L ICT preparation?

This independent study bank provides 100 practice MCQs organized across all seven official syllabus modules. Each question features detailed computing explanations and specific rationale for why incorrect choices are wrong, reinforcing both conceptual understanding and exam test-taking strategies.