3.2 Kirchhoff's Laws and Network Analysis

Why This Matters in Aviation Maintenance

While simple series and parallel rules allow us to analyze basic circuits, aircraft wiring networks are frequently far more complex. Modern aircraft electrical distribution systems feature interconnected busbars, cross-feed relays, redundant power paths, and bridge sensors that cannot be solved by simply summing resistances. To analyze these complex, multi-loop configurations, an aircraft technician must master Kirchhoff's Laws. These laws form the foundation for all advanced network analysis, allowing you to calculate the exact current and voltage drop in any branch of a multi-source system.

Kirchhoff's Current Law (KCL)

Also known as Kirchhoff's First Law or the Junction Rule, KCL states that the algebraic sum of all currents entering and leaving any node (junction point) in a circuit is exactly zero.

Mathematically, this is expressed as:

Sum of I_in = Sum of I_out

Or, assigning positive signs to currents entering the node and negative signs to currents leaving the node:

Sum of I = 0

Physical Basis: Conservation of Charge

KCL is a direct consequence of the Law of Conservation of Charge. In a closed electrical circuit, charge cannot accumulate at any node, nor can it be destroyed. Every coulomb of electrical charge that enters a junction must leave it in the same unit of time.

Example: If a busbar junction has three incoming wires carrying 5 A, 3 A, and 2 A respectively, the outgoing wire or wires must carry a total of 10 A. If one outgoing wire carries 6 A, the remaining outgoing wire must carry 4 A.

Kirchhoff's Voltage Law (KVL)

Also known as Kirchhoff's Second Law or the Loop Rule, KVL states that the algebraic sum of all potential differences (voltages) around any closed loop in a circuit must equal zero.

Mathematically, this is expressed as:

Sum of V = 0

Which implies:

Sum of V_sources = Sum of V_drops

Physical Basis: Conservation of Energy

KVL is based on the Law of Conservation of Energy. Voltage represents electrical potential energy per unit charge. If a charge starts at any point in a closed loop and travels completely around that loop, it must return to the same energy level when it reaches the starting point. Thus, the energy gained from voltage sources (rises) must exactly equal the energy lost in resistors (drops).

Sign Convention Rules for KVL:

When writing loop equations, a consistent path direction (clockwise or counter-clockwise) must be chosen. The following sign rules apply:

1. Voltage Sources: When traversing a battery or generator from the negative (-) to the positive (+) terminal, the voltage is a rise (+). Going from positive (+) to negative (-) represents a drop (-).
2. Resistors: When traversing a resistor in the direction of the assumed current, the voltage (I * R) is a drop (-). If traversing a resistor against the direction of the assumed current, the voltage is a rise (+).

Voltage Dividers

A voltage divider is a simple series circuit that scales down an input voltage to a lower output level. It is a critical component in aircraft sensor interfaces, logic level converters, and instrument calibration.

Unloaded Voltage Divider

For a basic series circuit with two resistors, R_1 and R_2, where the output voltage (V_out) is measured across R_2:

V_out = V_in * (R_2 / (R_1 + R_2))

Example: A 24 V DC bus supplies a voltage divider with R_1 = 100 Ohms and R_2 = 200 Ohms.

V_out = 24 V * (200 / (100 + 200)) = 24 * (200 / 300) = 16 V

Loaded Voltage Divider (The Loading Effect)

In practice, V_out is connected to a load resistor (R_L). This creates a parallel network between R_2 and R_L. The equivalent resistance of this lower branch is:

R_2p = (R_2 * R_L) / (R_2 + R_L)

Since R_2p is always smaller than R_2, the overall resistance ratio changes, causing the actual V_out under load to drop:

V_out(loaded) = V_in * (R_2p / (R_1 + R_2p))

When troubleshooting sensor circuits, remember that a high-impedance multimeter has a very large internal resistance (R_L ≈ 10 M-Ohms) and will not load the circuit significantly. However, if the output is connected to a low-resistance actuator or indicator, the voltage will sag dramatically.

Combined Series-Parallel Network Analysis

To analyze a complex network with both series and parallel elements, use the systematic reduction method:

1. Identify Parallel Groups: Find resistors that share the exact same two nodes and simplify them into a single equivalent resistance.
2. Combine Series Elements: Combine resistors that share a common current path with no junctions in between.
3. Redraw the Circuit: Redraw the circuit after each reduction step to avoid mapping errors.
4. Solve for Total Values: Once the circuit is reduced to a single equivalent resistance, calculate the total current using Ohm's Law.
5. Work Backwards: Use the calculated total current to determine individual branch voltages and currents by reversing the reduction steps.

Worked Exam Scenario: Combined Network

A circuit consists of a 24 V DC battery. In series with the battery is resistor R_1 = 4 Ohms. After R_1, the circuit branches into two parallel paths: R_2 = 12 Ohms and R_3 = 6 Ohms.

1. Simplify the Parallel Branch (R_23): R_23 = (R_2 * R_3) / (R_2 + R_3) = (12 * 6) / (12 + 6) = 72 / 18 = 4 Ohms
2. Calculate Total Resistance (R_total): R_total = R_1 + R_23 = 4 + 4 = 8 Ohms
3. Calculate Total Current (I_total): I_total = V_source / R_total = 24 / 8 = 3 A
4. Calculate Voltage Drop across R_1 (V_R1): V_R1 = I_total * R_1 = 3 * 4 = 12 V
5. Calculate Voltage across Parallel Branch (V_23): V_23 = V_source - V_R1 = 24 - 12 = 12 V
6. Calculate Individual Branch Currents:
   • I_R2 = V_23 / R_2 = 12 / 12 = 1 A
   • I_R3 = V_23 / R_3 = 12 / 6 = 2 A
   • Verify with KCL: I_total = I_R2 + I_R3 => 3 A = 1 A + 2 A (Confirmed)

Exam Pitfalls and Tips

• Sign Conventions in Loop Analysis: The most common mistake in loop analysis is incorrectly assigning signs during KVL traversal. If you write your equation going against the assumed current flow of a resistor, it must be treated as a positive value (voltage rise).
• The Junction Identification Trap: On schematics, ensure crossing lines are actual junctions. A dot represents a junction (KCL applies), while crossing lines without a dot indicate no connection.