3.2 Design Review & Verification

3.2 Design Review & Verification

Quality engineering during product development relies on structured evaluation mechanisms to prevent design flaws from reaching production. Regulated industries (such as medical devices under FDA 21 CFR 820.30 and ISO 13485, or aerospace under AS9100) enforce strict design controls. Central to design governance are Phase Gate Processes, Formal Design Reviews, Design Verification, and Design Validation.

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1. The Phase Gate Development Process

The Phase Gate Process (also called a Stage-Gate framework) divides product development into discrete, sequential stages separated by formal evaluation checkpoints called Gates.

+---------+    +--------+    +---------+    +--------+    +---------+    +--------+    +------------+
| Stage 1 |--> | Gate 1 |--> | Stage 2 |--> | Gate 2 |--> | Stage 3 |--> | Gate 3 |--> | Stage 4    |
| Concept |    | Review |    | Design  |    | Review |    | Pilot   |    | Review |    | Production |
+---------+    +--------+    +---------+    +--------+    +---------+    +--------+    +------------+

At each gate, a cross-functional governance board evaluates project deliverables against predefined exit criteria. The gate review yields one of four decisions:

1. Go: Project meets all criteria and proceeds to the next phase.
2. Kill: Project is canceled due to technical failure, excessive cost, or market unfeasibility.
3. Hold: Project is paused pending external factors or resource availability.
4. Recycle / Redo: Project remains in the current stage until specific action items or missing criteria are completed.

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2. Stages of Formal Design Review

A Design Review is a documented, comprehensive, and systematic examination of a design to evaluate its capability to meet requirements and identify potential problems. Formal design reviews occur at critical milestones:

Multi-Disciplinary Team Composition

According to ISO 9001 and FDA regulations, design reviews MUST include representatives from all functions affected by the design stage being reviewed (Design, Quality, Manufacturing, Regulatory, Reliability, Field Support) AND at least one independent reviewer who is not directly responsible for the design stage under review.

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3. Design Verification vs. Design Validation

One of the most frequently tested concepts on the ASQ CQE exam is the fundamental distinction between Verification and Validation.

+-----------------------------------------------------------------------------------+
|                                DESIGN CONTROLS                                    |
+-----------------------------------------+-----------------------------------------+
|          DESIGN VERIFICATION            |            DESIGN VALIDATION            |
+-----------------------------------------+-----------------------------------------+
| "Did we design the product RIGHT?"      | "Did we design the RIGHT product?"      |
| Evaluates: Output vs. Input Specs       | Evaluates: Output vs. User Needs        |
| Focus: Quantitative engineering specs   | Focus: Qualitative user operating needs |
| Environment: Laboratory / Test bench    | Environment: Actual / Simulated field   |
| Units: Prototypes, subassemblies, code  | Units: Production-equivalent units      |
+-----------------------------------------+-----------------------------------------+

Detailed Comparison Table

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4. Test Plan Development & Statistical Protocol

Quality engineers lead the development of Verification and Validation Test Plans. A robust test plan must specify:

1. Test Objective: Clear statement of the feature or spec being verified.
2. Acceptance Criteria: Unambiguous quantitative limits (e.g., "Tensile strength $\ge 450 \text{ MPa}$ at $23^\circ\text{C}$").
3. Sample Size & Statistical Rationale: Sample sizes must be statistically justified based on risk, confidence levels ($1 - \alpha$), and reliability targets ($1 - \beta$).
4. Environmental Conditions: Operating temperature, humidity, vibration, and thermal shock parameters.
5. Traceability Matrix: Mapping every test protocol back to specific design input requirements.

Statistical Sample Size Rationale Example

For a verification test evaluating a continuous normal variable with unknown variance, the required sample size $n$ to estimate a parameter within margin of error $E$ at confidence level $Z_{1-\alpha/2}$ is:

$n = \left( \frac{Z_{1-\alpha/2} \cdot s}{E} \right)^2$

Where $s$ is the estimated standard deviation from historical prototype data. If test sample size is restricted, tolerance intervals or binomial success-run formulas ($n = \frac{\ln(1 - C)}{\ln(R)}$) are used to prove reliability $R$ at confidence $C$.

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5. CQE Exam Tips & Key Pitfalls

[!IMPORTANT] Remember the exact definitions for the exam: Verification compares Design Output to Design Input (engineering specifications). Validation compares Design Output to User Needs and Intended Use. Always ensure that validation testing is performed on production-equivalent units under actual or simulated operating environments.