100+ Free Cameroon GCE A-Level Computer Science (0795) Practice Questions

Prepare for the Cameroon General Certificate of Education Advanced Level Computer Science (Syllabus 0795) exam with instant access — no signup required.

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44.93% pass rate in the June 2026 session (Cameroon GCE Board, Performance by Subjects, results released 21 August 2026) Pass Rate

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Key Facts: Cameroon GCE A-Level Computer Science (0795) Exam

0795

Official CGCEB Subject Code for Advanced Level Computer Science

Cameroon GCE Board Syllabus Regulations

3 Papers

Assessment Structure (Paper 1 MCQ, Paper 2 Theory, Paper 3 Practical Lab)

CGCEB Scheme of Assessment

170 Marks

Total Combined Raw Marks across Papers 1, 2, and 3

Cameroon GCE Board Examination Blueprint

A to E

Official GCE Advanced Level Passing Grades (Grade A highest to Grade E pass)

Cameroon GCE Board Grading System

100

High-Quality Practice Questions in this OpenExamPrep Revision Bank

OpenExamPrep

Cameroon GCE A-Level Computer Science 0795 is assessed by the Cameroon GCE Board via three papers: Paper 1 (50 compulsory MCQs, 1h30m), Paper 2 (theory, 2h30m) and a separately scheduled practical laboratory examination. This 100-question practice test provides comprehensive preparation across all official syllabus modules for 2026.

Sample Cameroon GCE A-Level Computer Science (0795) Practice Questions

Try these sample questions to test your Cameroon GCE A-Level Computer Science (0795) exam readiness. Each question includes a detailed explanation. Start the interactive quiz above for the full 100+ question experience with AI tutoring.

1In computer processor architecture, what is the defining structural difference between the Harvard architecture and the Von Neumann architecture?

A.Harvard architecture uses physically separate memory units and buses for instructions and data, whereas Von Neumann uses unified memory and buses for both.

B.Von Neumann architecture utilizes separate arithmetic pipelines for integer and floating-point operations, whereas Harvard combines them.

C.Harvard architecture requires all instructions to execute in a single clock cycle, whereas Von Neumann uses multi-cycle microcode.

D.Von Neumann architecture uses direct-mapped caches exclusively, whereas Harvard architecture supports fully associative caches.

Explanation: Harvard architecture incorporates physically distinct storage and signal pathways (buses) for instructions and data, allowing simultaneous instruction fetch and data read/write. In contrast, Von Neumann architecture uses a unified memory space and shared system bus for both instructions and data, which can create a data transfer bottleneck known as the Von Neumann bottleneck.

2During the CPU fetch-decode-execute cycle, what is the primary role of the Program Counter (PC)?

A.It holds the current machine instruction being decoded and executed by the Control Unit.

B.It stores the memory address of the next instruction to be fetched and executed.

C.It records arithmetic status flags such as zero, carry, sign, and overflow resulting from ALU operations.

D.It temporarily stores operand data transferred between main memory and the Arithmetic Logic Unit.

Explanation: The Program Counter (PC), also called the Instruction Pointer, holds the memory address of the next sequential instruction to be fetched from memory. Once the address is copied to the Memory Address Register (MAR), the PC is automatically incremented or updated to a branch target.

3During a memory read operation in the fetch cycle, how do the Memory Address Register (MAR) and Memory Data Register (MDR) interact with the system buses?

A.MAR places data onto the data bus while MDR receives the target address from the address bus.

B.MAR holds the address placed onto the address bus, while MDR latches the data returned from memory via the data bus.

C.MAR decodes the operation code while MDR sends control signals over the control bus to synchronize RAM.

D.Both MAR and MDR send parallel 64-bit addresses over the address bus to achieve interleaved memory access.

Explanation: The MAR is directly connected to the unidirectional address bus and holds the physical memory location to be accessed. The MDR (or Memory Buffer Register) is connected to the bidirectional data bus and holds the data word or instruction fetched from that memory address.

4In a standard accumulator-based CPU architecture, which sequence of Register Transfer Level (RTL) micro-operations correctly represents the instruction fetch phase?

A.MAR <- [PC]; PC <- [PC] + 1; MDR <- Memory[MAR]; CIR <- [MDR]

B.MDR <- [PC]; MAR <- [MDR]; CIR <- Memory[MAR]; PC <- [PC] + 1

C.CIR <- [PC]; MAR <- [CIR]; MDR <- Memory[MAR]; PC <- [MDR]

D.MAR <- [ACC]; MDR <- Memory[MAR]; PC <- [PC] + 1; CIR <- [MDR]

Explanation: The fetch phase begins by transferring the address from the PC into the MAR (`MAR <- [PC]`). Simultaneously or immediately after, the PC is incremented (`PC <- [PC] + 1`), the instruction word is read from memory into the MDR (`MDR <- Memory[MAR]`), and finally the instruction is copied into the Current Instruction Register (`CIR <- [MDR]`) for decoding.

5A processor has a 32-bit address bus and byte-addressable physical memory. What is the maximum physical memory capacity that this processor can directly address?

A.512 Megabytes (512 MB)

B.2 Gigabytes (2 GB)

C.4 Gigabytes (4 GB)

D.16 Gigabytes (16 GB)

Explanation: With an n-bit address bus, a processor can address 2^n unique memory locations. For a 32-bit address bus, 2^32 = 4,294,967,296 distinct byte addresses, which equals exactly 4 Gigabytes (4 GB) of addressable memory.

6A computer system uses 16-bit byte-level memory addresses and a direct-mapped cache of 4 KB total data capacity with 64-byte cache blocks (lines). How are the 16 address bits partitioned into Tag, Line Index, and Block Offset fields?

A.Tag = 4 bits, Line Index = 6 bits, Block Offset = 6 bits

B.Tag = 6 bits, Line Index = 6 bits, Block Offset = 4 bits

C.Tag = 5 bits, Line Index = 6 bits, Block Offset = 5 bits

D.Tag = 6 bits, Line Index = 4 bits, Block Offset = 6 bits

Explanation: With 64-byte blocks, the Block Offset requires log2(64) = 6 bits. The cache has 4 KB / 64 B = 4096 / 64 = 64 lines (slots), requiring log2(64) = 6 bits for the Line Index. The remaining bits form the Tag: 16 - (6 + 6) = 4 bits. Thus: Tag = 4 bits, Index = 6 bits, Offset = 6 bits.

7What is the principal operational reason that Static RAM (SRAM) is used for CPU cache memory while Dynamic RAM (DRAM) is used for main system memory?

A.SRAM uses capacitor storage requiring periodic refresh cycles, offering very high density at low cost.

B.SRAM uses flip-flop latch circuits that retain data without refreshing, providing faster access times despite lower density and higher cost per bit.

C.DRAM retains its state indefinitely without electrical power, making it ideal for persistent operating system loading.

D.DRAM operates synchronously with the system bus clock whereas SRAM operates purely asynchronously without clock signals.

Explanation: SRAM utilizes multi-transistor flip-flops (typically 6 transistors per cell) to store each bit. Because it does not rely on leaking capacitors, it requires no refresh circuitry, achieving nanosecond access times suitable for L1/L2 caches, whereas DRAM uses single-transistor/capacitor cells that are cheaper and denser for large main memory.

8In a virtual memory system using demand paging, what primary condition causes severe thrashing to occur?

A.The Translation Lookaside Buffer (TLB) reaches full capacity and stops caching page table entries.

B.The sum of the working sets of active processes exceeds available physical RAM frames, causing the OS to spend more time swapping pages than executing instructions.

C.The operating system scheduler assigns equal CPU time slices to I/O-bound and CPU-bound processes.

D.The CPU executes non-maskable hardware interrupts faster than the disk controller can service them.

Explanation: Thrashing occurs when the resident memory is insufficient to hold the active working sets of all executing processes. As a result, page faults occur continuously, and the CPU spends virtually all its time waiting for high-latency disk paging operations rather than executing user instructions.

9In a pipelined CPU, which type of hazard occurs when an instruction depends on the data result of an immediately preceding instruction that has not yet completed its write-back stage?

A.Structural hazard

B.Control hazard (branch hazard)

C.Data hazard (Read-After-Write)

D.Arbitration hazard

Explanation: A data hazard (specifically Read-After-Write or RAW) occurs when an instruction in the decode or execute stage requires an operand value that is currently being computed by an earlier instruction in the pipeline before it has been written back to the register file.

10Which architectural characteristic is fundamentally distinctive of Reduced Instruction Set Computers (RISC) compared to Complex Instruction Set Computers (CISC)?

A.RISC relies heavily on variable-length instructions with complex memory-to-memory addressing modes.

B.RISC utilizes fixed-length single-cycle instructions with a load-store architecture and extensive general-purpose registers.

C.CISC processors eliminate microcode and execute all operations directly in hardwired control logic.

D.RISC designs incorporate specialized hardware instructions for high-level language loops and polynomial evaluation.

Explanation: RISC architectures emphasize simple, fixed-length instructions that execute in a single clock cycle, utilizing a load-store model where memory access is strictly isolated to explicit LOAD and STORE instructions, operating primarily on a large register set.

About the Cameroon GCE A-Level Computer Science (0795) Exam

The Cameroon GCE Advanced Level Computer Science (Subject Code 0795) is a two-year senior secondary academic qualification administered by the Cameroon GCE Board. It equips Upper Sixth students with rigorous foundations in computer architecture, data structures, algorithm design, software engineering, operating systems, networking, relational database management, and cyber legislation. Assessment comprises three papers: Paper 1 (MCQs), Paper 2 (Theory), and Paper 3 (Practical Programming). Format note: this site's practice bank is 100 four-option multiple-choice questions covering the whole official syllabus. Paper 1 of the real examination is genuinely multiple choice (50 compulsory questions), so the format matches that paper, but the bank is a study aid only — it does not simulate the written theory/essay paper(s) or any practical examination, and its length does not describe the official exam.

Assessment

Official Advanced Level structure for subject code 0795 (Computer Science) per the Cameroon GCE Board June 2026 timetable (Form G6): Paper 1: 50 compulsory multiple-choice questions (1 hour 30 minutes); Paper 2: written theory/structured questions (2 hours 30 minutes); a separately scheduled practical examination (practical phase, 5–27 May 2026). Total written time is 4 hours. The Board does not publish per-paper mark weightings for individual subjects.

Time Limit

Paper 1: 1 hour 30 minutes; total written time 4 hours plus a separately scheduled practical examination.

Passing Score

Grade E or better (Cameroon GCE Advanced Level grades A, B, C, D and E are passes; O is a subsidiary pass and F is a fail)

Exam Fee

17,000 FCFA (Cameroon General Certificate of Education Board (CGCEB), Buea, Cameroon)

Cameroon GCE A-Level Computer Science (0795) Exam Content Outline

20%

Computer Systems, Architecture & Low-Level Operations

CPU functional units (ALU, CU, internal registers including PC, MAR, MDR, CIR, ACC), the fetch-decode-execute machine cycle, address/data/control bus operations, memory hierarchy (L1/L2/L3 cache, SRAM, DRAM, virtual memory paging), assembly language structure, two-pass assembler algorithms, Boolean theorems, Karnaugh maps, combinational logic (half/full adders, 4-to-1 multiplexers), sequential flip-flops, and binary data representations (two's complement, IEEE 754 floating point standard).

25%

Data Structures & Algorithms

Linear data structures including multi-dimensional arrays (row-major and column-major memory mapping), singly and doubly linked lists, stack operations and applications (infix-to-postfix conversion, postfix evaluation), and circular queues; non-linear data structures including binary search trees (insert, delete, in-order/pre-order/post-order traversals) and graphs (adjacency matrix vs list, BFS, DFS, Dijkstra's algorithm); algorithm design, searching techniques (linear, binary), sorting methods (bubble, insertion, selection, merge, quicksort), asymptotic Big-O time and space complexity analysis, and recursive vs iterative execution models.

20%

Software Engineering & Programming Paradigms

Software Development Life Cycle (SDLC) stages (feasibility, requirements specification, design, implementation, testing, maintenance), process models (Waterfall, V-Model, Spiral risk management, Agile Scrum sprints, Extreme Programming), programming paradigms (imperative, functional, declarative, object-oriented), core OOP principles (encapsulation, inheritance, runtime polymorphism, dynamic dispatch, abstract classes, interfaces), software testing techniques (black-box boundary value analysis, white-box cyclomatic complexity, unit/integration/system testing), and language translators (phases of a compiler: lexical analysis, syntax parsing, semantic type-checking, code generation).

20%

Systems Software, Operating Systems & Networks

Operating system architecture, user vs kernel mode, system calls, interrupt handling routines, process management (PCB, 5-state process lifecycle), CPU scheduling algorithms (FCFS, SJF, Round Robin, SRTF), inter-process communication, semaphores, race conditions, deadlock conditions and Banker's algorithm, memory management (paging, page replacement algorithms including FIFO and LRU, thrashing), network topologies, the 7-layer OSI and TCP/IP models, IPv4/IPv6 addressing and subnetting calculations, transport protocols (TCP 3-way handshake vs UDP), network security (symmetric AES vs asymmetric RSA cryptography, digital certificates), and firewalls.

15%

Databases & Social/Legal Implications

Relational database concepts (relations, candidate/primary/foreign keys, entity and referential integrity), Entity-Relationship (ER) modeling, normalization techniques (1NF, 2NF, 3NF, BCNF) to eliminate data redundancy and anomalies, SQL queries (DDL, DML, aggregate functions, nested subqueries, inner/outer joins), database transaction ACID properties and concurrency control, Cameroon cybersecurity legislation (Law No. 2010/012 on cybersecurity and cybercrime), the regulatory role of ANTIC, open source vs proprietary software licenses, and professional computer ethics.

How to Pass the Cameroon GCE A-Level Computer Science (0795) Exam

What You Need to Know

Passing score: Grade E or better (Cameroon GCE Advanced Level grades A, B, C, D and E are passes; O is a subsidiary pass and F is a fail)
Assessment: Official Advanced Level structure for subject code 0795 (Computer Science) per the Cameroon GCE Board June 2026 timetable (Form G6): Paper 1: 50 compulsory multiple-choice questions (1 hour 30 minutes); Paper 2: written theory/structured questions (2 hours 30 minutes); a separately scheduled practical examination (practical phase, 5–27 May 2026). Total written time is 4 hours. The Board does not publish per-paper mark weightings for individual subjects.
Time limit: Paper 1: 1 hour 30 minutes; total written time 4 hours plus a separately scheduled practical examination.
Exam fee: 17,000 FCFA

Keys to Passing

Work through all 100 available questions
Review every answer and explanation
Track weak areas and revisit them
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Cameroon GCE A-Level Computer Science (0795) Study Tips from Top Performers

1Master step-by-step binary arithmetic, Two's complement representation, and IEEE 754 floating-point format conversions, ensuring you show complete working during practice.

2Practice drawing and simplifying Karnaugh maps for 3-variable and 4-variable Boolean expressions, paying special attention to Don't Care groupings and minimal SOP forms.

3Trace algorithms systematically using structured trace tables, recording variable states across nested loops, recursive stack frames, and array element swaps.

4Work extensively on database normalization problems, clearly stating functional dependencies and verifying that relations satisfy 1NF, 2NF, 3NF, and BCNF without data redundancy.

5Review IPv4 subnetting formulas to quickly determine subnet masks, network addresses, broadcast addresses, and valid host ranges under CIDR slash notation.

6Familiarize yourself with Cameroon Law No. 2010/012 and ANTIC mandates regarding cyber offences, data privacy, and digital security certification.

Frequently Asked Questions

What is the structure of the Cameroon GCE A-Level Computer Science (0795) examination?

The examination consists of three compulsory components per the Cameroon GCE Board June 2026 timetable: Paper 1 is a 1-hour 30-minute multiple-choice paper with 50 compulsory questions; Paper 2 is a 2-hour 30-minute structured theory and problem-solving paper; and there is a separately scheduled practical software development examination conducted in a computer laboratory during the Board's practical phase (5–27 May 2026). The Board does not publish per-paper mark weightings.

What programming languages are assessed in Paper 3 Practical Software Development?

The Cameroon GCE Board syllabus allows approved structured and object-oriented high-level programming languages in Paper 3, predominantly C, C++, Java, and Python. Candidates are expected to implement algorithms, handle file operations, manipulate data structures, and debug functional programs in an approved IDE environment.

How is the final grade determined for Cameroon GCE A-Level Computer Science?

The composite mark across Paper 1, Paper 2, and Paper 3 is weighted and graded on the standard Cameroon GCE A-Level scale: Grade A (highest distinction, 5 points), Grade B (4 points), Grade C (3 points), Grade D (2 points), Grade E (minimum pass, 1 point), Grade O (Ordinary Level subsidiary pass, 0 points), and Grade F (Fail, 0 points).

What are the registration fees for GCE A-Level Computer Science?

Official CGCEB registration entails a base registration fee of 9,000 FCFA, a subject fee of 2,000 FCFA, a practical examination fee of 5,000 FCFA (specific to subjects with lab components), and a 1,000 FCFA Form G3/ICT fee, totaling approximately 17,000 FCFA for single-subject entry.

Does this practice test replicate the official Cameroon GCE Board examination?

This resource provides 100 original, high-quality practice multiple-choice questions aligned with the official 0795 syllabus. It serves as an academic revision tool designed to help students master core computational theory, numerical calculations, logic circuits, and algorithmic problem-solving.

What Cameroonian laws and regulatory bodies are covered in the 0795 syllabus?

The syllabus covers Law No. 2010/012 of 21 December 2010 relating to cybersecurity and cybercrime in Cameroon, the regulatory enforcement and digital security functions of ANTIC (National Agency for Information and Communication Technologies), and ethical standards governing intellectual property and data protection.

100+ Free Cameroon GCE A-Level Computer Science (0795) Practice Questions

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