100+ Free Ruankao Embedded System Designer (Intermediate) Practice Questions

Prepare for the Computer Technology and Software Professional Qualification (Level) Examination — Intermediate Embedded System Designer (计算机技术与软件专业技术资格（水平）考试 — 中级嵌入式系统设计师) exam with instant access — no signup required.

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2026 Statistics

Key Facts: Ruankao Embedded System Designer (Intermediate) Exam

45/75

Passing score required on each of the two subjects in the same sitting

National 软考 fixed passing standard (60% of 75) cited in 深人考发〔2026〕7号

240 minutes

Combined CBT time for 基础知识 then 应用技术

软考 computer-based sitting rules for intermediate qualifications

23–26 May 2026

Upper-half-year 2026 sitting window; Embedded System Designer is not in the October list

计考办〔2026〕1号 / 深人考发〔2026〕7号

RMB 73/subject

Guangdong/Shenzhen fee example

粤发改价格函〔2024〕1073 via 深人考发〔2026〕7号

No score rollover

Both subjects must be passed together

软考 two-subject sitting rule

软考 Intermediate Embedded System Designer is a Chinese CBT qualification: knowledge MCQs plus an 应用技术 short-answer paper in one 240-minute sitting, 45/75 on each subject, no score rollover. The 2026 sitting is 23–26 May only. This 100-question English MCQ bank adapts MCU, RTOS, and hardware/software design judgment; it is not an official paper or a lab/JTAG substitute.

Sample Ruankao Embedded System Designer (Intermediate) Practice Questions

Try these sample questions to test your Ruankao Embedded System Designer (Intermediate) exam readiness. Each question includes a detailed explanation. Start the interactive quiz above for the full 100+ question experience with AI tutoring.

1What is the unsigned decimal value of the 8-bit binary pattern 11010110?

A.182

B.198

C.214

D.246

Explanation: Unsigned 11010110 equals 128+64+16+4+2 = 214. Each 1 contributes its place value: 2^7, 2^6, 2^4, 2^2, and 2^1. 软考基础知识 items routinely ask this conversion without a calculator.

2Convert hexadecimal 0x2A to decimal.

A.26

B.42

C.52

D.162

Explanation: Hexadecimal 0x2A is 2×16 + 10 = 42 because A is ten. The same value is binary 00101010. Mixing hex digit values with decimal place weights is a common 软考 trap.

3Which 8-bit two's-complement encoding represents decimal −13?

A.00001101

B.10001101

C.11110010

D.11110011

Explanation: Write +13 as 00001101, invert the bits to 11110010 (one's complement), then add 1 to obtain 11110011. Sign-magnitude 10001101 and the inverted pattern without the +1 are the usual distractors on 软考 numeric items.

4What is the representable range of 8-bit two's-complement integers?

A.−128 to +127

B.−127 to +127

C.−128 to +128

D.0 to 255

Explanation: In n-bit two's complement the range is −2^(n−1) through +2^(n−1)−1. For n=8 that is −128 to +127. There is one more negative value than positive because 10000000 is −128 and has no positive counterpart.

5A processor uses a perfectly balanced 5-stage pipeline with no hazards or stalls. How many clock cycles does it take to complete 100 instructions, assuming one instruction enters the pipeline per cycle after fill?

A.100

B.104

C.500

D.20

Explanation: The first instruction occupies 5 cycles (fill). Each of the remaining 99 instructions completes one cycle later, so total cycles = 5 + 99 = 104, equivalently k+(n−1) for k stages and n instructions. Non-pipelined execution would take 100×5 = 500 cycles.

6An even-parity bit is appended to the 7-bit data 1011011. What is the parity bit?

A.0

B.1

C.X (don't care)

D.The MSB of the data

Explanation: Even parity makes the total number of 1s even, including the parity bit. 1011011 has five 1s (odd), so the parity bit must be 1 to make six 1s. Odd count of 1s in the data is the cue to set even-parity to 1.

7A firmware designer must move 4096 ADC samples from a peripheral FIFO into SRAM with the least CPU involvement per sample. Which I/O control method is the best fit?

A.DMA (direct memory access)

B.Programmed I/O polling in a tight CPU loop

C.Memory-mapped register reads from the main thread only

D.Interrupt-driven transfer of one sample per ISR with no DMA

Explanation: DMA lets a controller transfer blocks between a peripheral and memory after the CPU programs source, destination, and count. Polling and per-sample ISRs keep the CPU in the path for every word. Memory-mapped I/O is how the registers are addressed, not a bulk-offload method by itself.

8After a cache miss on address 0x2000, the next sequential instruction fetch at 0x2004 hits. Which locality property is this primarily illustrating?

A.Temporal locality only

B.Write-back allocation

C.Compulsory-miss elimination by associativity

D.Spatial locality

Explanation: Spatial locality is the tendency to access addresses near a recent access. A cache line fill brings a block of neighboring words, so 0x2004 can hit after 0x2000 missed. Temporal locality is reuse of the same address over time, which this stem does not show.

9A 16 KiB direct-mapped cache has 32-byte lines. How many bits are used for the line offset and the index (set) field of a byte address?

A.Offset 4 bits, index 8 bits

B.Offset 5 bits, index 9 bits

C.Offset 5 bits, index 10 bits

D.Offset 6 bits, index 8 bits

Explanation: Line size 32 bytes ⇒ offset = log2(32) = 5 bits. Number of lines = 16 KiB / 32 B = 16384/32 = 512, so index = log2(512) = 9 bits. Direct-mapped means one line per set, so sets equal lines.

10In synchronous digital design, how does a positive-edge-triggered D flip-flop differ from a level-sensitive D latch?

A.The flip-flop samples D continuously while CLK is high; the latch samples only on the rising edge

B.Both sample D only on the falling edge of CLK

C.The flip-flop captures D at the rising clock edge; the latch is transparent while the enable is active

D.The latch stores two bits; the flip-flop stores one

Explanation: A D latch is transparent for the whole time its enable (often CLK) is at the active level, so D can race through. An edge-triggered D flip-flop samples D only at the clock edge, which is why sequential timing analysis uses setup and hold around that edge.

About the Ruankao Embedded System Designer (Intermediate) Exam

The Ruankao Intermediate Embedded System Designer exam (软考中级嵌入式系统设计师) is a national computer-technology qualification under MIIT and MOHRSS. Official 考试说明 (https://www.ruankao.org.cn/article/content/bkzn/02_35.html) requires computer science fundamentals; embedded hardware and software; analysis methods; design and development steps; implementation; operations and maintenance; informatization; IT standards, security, and law; technology trends; and English reading of computer and embedded materials. Qualified candidates design hardware and software from an overall specification, write development documentation, guide implementation and debug, and perform optimization and integration test at engineer level. The 2026 sitting is in the upper-half window 23–26 May 2026 only per 计考办〔2026〕1号 / 深人考发〔2026〕7号 (this qualification is not listed in the lower-half window). Delivery is computer-based in Chinese: two subjects in one sitting, combined 240 minutes. Both papers must reach 45/75; scores do not roll. There is no education or experience restriction under 国人部发〔2003〕39号. Fees are set provincially. This OpenExamPrep bank is an English-language MCQ study adaptation of knowledge and design judgment, not an official translation, a lab, or a JTAG substitute.

Assessment

Computer-based combined sitting of 240 minutes. 基础知识: maximum 120 minutes and minimum 90 minutes. Remaining time is 嵌入式系统设计应用技术. Candidates who will not sit 应用技术 may leave after 120 minutes; those continuing may leave 60 minutes before the end. Both subjects must reach 45/75 in the same sitting; scores do not roll.

Time Limit

240 minutes combined

Passing Score

45/75 each subject

Exam Fee

Provincially set (e.g. Guangdong/Shenzhen RMB 73/subject per 粤发改价格函〔2024〕1073 and 深人考发〔2026〕7号) (MIIT & MOHRSS / ruankao.org.cn)

Ruankao Embedded System Designer (Intermediate) Exam Content Outline

15%

computer-science-and-digital-logic

Number systems, two's complement, Boolean and sequential timing, pipeline/cache/I/O control, and reliability/check-code calculations from the official 考试说明

22%

embedded-hardware-mcu-memory-io

MCU architecture (especially ARM Cortex-M), memory types, buses, GPIO/UART/SPI/I2C/CAN, ADC/DAC/PWM/DMA, interrupt/NVIC, and clock/reset/watchdog/power

22%

embedded-software-rtos

Embedded C, volatile and ISR rules, cross-compilation and linker map, RTOS tasks, preemptive priority scheduling, mutex/semaphore/queues, and priority inversion

18%

analysis-design-development-process

Requirements, hardware/software partitioning and co-design, state machines, V-model/lifecycle, architecture/HAL, and development documentation steps

13%

implementation-test-maintenance

Implementation and debug judgment (including JTAG/SWD knowledge, not lab operation), unit/integration/system test, firmware update, and operations/maintenance

10%

standards-security-law-trends

Informatization familiarity, IT standards, security, PRC software/copyright law, embedded technology trends, and English reading of computer/embedded materials

How to Pass the Ruankao Embedded System Designer (Intermediate) Exam

What You Need to Know

Passing score: 45/75 each subject
Assessment: Computer-based combined sitting of 240 minutes. 基础知识: maximum 120 minutes and minimum 90 minutes. Remaining time is 嵌入式系统设计应用技术. Candidates who will not sit 应用技术 may leave after 120 minutes; those continuing may leave 60 minutes before the end. Both subjects must reach 45/75 in the same sitting; scores do not roll.
Time limit: 240 minutes combined
Exam fee: Provincially set (e.g. Guangdong/Shenzhen RMB 73/subject per 粤发改价格函〔2024〕1073 and 深人考发〔2026〕7号)

Keys to Passing

Work through all 100 available questions
Review every answer and explanation
Track weak areas and revisit them
Use our AI tutor for tough concepts

Ruankao Embedded System Designer (Intermediate) Study Tips from Top Performers

1Drill binary/hex conversions, two's-complement arithmetic, pipeline cycle counts, and timer/ADC numeric items until they are automatic — 软考基础知识 rewards calculation, not only definitions.

2On interface items, map UART (async, no shared clock), SPI (full-duplex master/slave), I2C (open-drain addressed bus), and CAN (differential, ID arbitration) to the constraint in the stem.

3Treat RTOS items as design judgment: mutex for exclusive ownership, semaphore for signaling or counting resources, queues for data, and never block in an ISR.

4For 应用技术-style cases, state hardware/software partition, task/ISR split, and the first debug observation (clock, reset, rails) before naming a tool.

5Do not skip 了解-level law and English items — 计算机软件保护条例 (ideas not protected; legal-person term 50 years from first publication) and terminology matching are short but scored.

Frequently Asked Questions

What is the Ruankao Intermediate Embedded System Designer qualification?

It is the Intermediate Embedded System Designer subject (中级嵌入式系统设计师) in the Computer Technology and Software Professional Qualification (Level) Examination (软考). Official 考试说明: https://www.ruankao.org.cn/article/content/bkzn/02_35.html. Passing confers the corresponding intermediate professional qualification (工程师 level).

How is the official exam structured and scored?

Two subjects are taken in one computer-based sitting totaling 240 minutes. 嵌入式系统基础知识 is a choice paper (CBT 基础知识: maximum 120 minutes, minimum 90 minutes). Remaining time is 嵌入式系统设计应用技术 (short-answer). Each subject is scored out of 75; both must reach 45 in the same sitting. Scores do not roll.

Who may sit the exam, and what does it cost?

There is no education or experience restriction under 国人部发〔2003〕39号. Fees are set by each province. Shenzhen/Guangdong charge RMB 73 per subject (深人考发〔2026〕7号 citing 粤发改价格函〔2024〕1073).

When is the 2026 sitting?

Embedded System Designer is offered in the upper-half-year window only. Provincial notices implementing 计考办〔2026〕1号 (including 深人考发〔2026〕7号) place the 2026 sitting on 23–26 May 2026; this qualification is not listed in the October window. Register through https://www.ruankao.org.cn/.

Why are these practice questions in English?

The official exam is in Chinese (officialLanguages: zh) and 嵌入式系统设计应用技术 is a written short-answer paper. This OpenExamPrep bank is an English-language MCQ study adaptation of syllabus knowledge and design judgment. It is not an official translation, not a CBT simulation, not a bench lab, and not a substitute for practicing Chinese 应用技术 write-ups or using JTAG/debug hardware.