CENEVAL EGEL Plus Ingeniería Electrónica (EGEL Plus IELECTRO)

A silicon NPN bipolar junction transistor (BJT) is configured in a voltage-divider common-emitter bias circuit with VCC = 12 V, R1 = 47 kΩ, R2 = 10 kΩ, RC = 2.2 kΩ, and RE = 1.0 kΩ. Assuming VBE = 0.7 V and base current is negligible (stiff divider), what are the approximate quiescent collector current ICQ and collector-emitter voltage VCEQ?

• AICQ ≈ 1.40 mA, VCEQ ≈ 7.50 V
• BICQ ≈ 2.10 mA, VCEQ ≈ 5.26 V
• CICQ ≈ 0.64 mA, VCEQ ≈ 9.96 V
• DICQ ≈ 1.40 mA, VCEQ ≈ 8.91 V

An N-channel enhancement MOSFET has a threshold voltage Vth = 1.2 V and conduction parameter k'n*(W/L) = 1.0 mA/V². If the device is biased with gate-to-source voltage VGS = 3.2 V and drain-to-source voltage VDS = 4.0 V, what is the drain current ID assuming channel-length modulation is negligible?

• A4.0 mA
• B2.0 mA
• C5.12 mA
• D8.0 mA

An ideal operational amplifier is connected in an inverting configuration with input resistor Rin = 4.7 kΩ and feedback resistor Rf = 47 kΩ. If an input signal Vin = +0.5 V is applied, what is the output voltage Vout and the input impedance seen by the source?

• AVout = -5.0 V, Zin = 4.7 kΩ
• BVout = +5.0 V, Zin = 47 kΩ
• CVout = -5.0 V, Zin = ∞
• DVout = -0.05 V, Zin = 4.7 kΩ

A sensor provides an analog voltage of 1.20 V that must be scaled to 12.0 V using a non-inverting op-amp amplifier. If the feedback resistor between output and inverting terminal is Rf = 90 kΩ, what resistance R1 must be placed between the inverting terminal and ground?

• A10 kΩ
• B9.0 kΩ
• C100 kΩ
• D1.0 kΩ

A summing operational amplifier has three input resistors R1 = 10 kΩ, R2 = 20 kΩ, and R3 = 50 kΩ connected to input voltages V1 = +1.0 V, V2 = -2.0 V, and V3 = +5.0 V respectively. If the feedback resistor is Rf = 100 kΩ, what is the output voltage Vout?

• A-10.0 V
• B+10.0 V
• C-20.0 V
• D0.0 V

In a standard four-resistor operational amplifier difference amplifier (subtractor) with inputs V1 (to inverting branch via R1) and V2 (to non-inverting branch via R3), what exact resistor matching relationship must be satisfied to achieve an ideal common-mode rejection ratio (CMRR = ∞)?

• ARf / R1 = R4 / R3
• BRf + R1 = R4 + R3
• CRf * R1 = R4 * R3
• DRf - R1 = R4 - R3

An operational amplifier has a slew rate SR = 0.50 V/μs. What is the maximum frequency (full-power bandwidth fmax) of a sinusoidal output signal with a peak amplitude of Vp = 5.0 V that can be reproduced without slew-rate distortion?

• A15.9 kHz
• B31.8 kHz
• C100.0 kHz
• D7.95 kHz

An active first-order low-pass filter is implemented using an operational amplifier with an input resistor R = 10.0 kΩ and a feedback capacitor C = 15.9 nF connected in parallel with a feedback resistor Rf = 10.0 kΩ. What is the cutoff frequency (-3 dB frequency fc) of this filter?

• A1.0 kHz
• B6.28 kHz
• C15.9 kHz
• D100 Hz

A second-order Sallen-Key low-pass filter is designed with a maximally flat passband response (Butterworth approximation). What are the damping ratio zeta, quality factor Q, and high-frequency stopband attenuation roll-off rate of this filter?

• Azeta = 0.707, Q = 0.707, roll-off = -40 dB/decade
• Bzeta = 1.000, Q = 0.500, roll-off = -20 dB/decade
• Czeta = 0.500, Q = 1.000, roll-off = -60 dB/decade
• Dzeta = 0.000, Q = ∞, roll-off = -40 dB/decade

A through-hole resistor on a prototype board has the four color bands yellow, violet, red, gold. What are its nominal resistance and tolerance?

• A4.7 kΩ ± 5%
• B47 kΩ ± 5%
• C472 Ω ± 10%
• D4.7 kΩ ± 10%

In a Wien-bridge sine-wave oscillator using an op-amp, the lead-lag RC bridge network has identical resistors R = 10 kΩ and capacitors C = 10 nF. According to the Barkhausen criterion, what are the oscillation frequency f0 and the required non-inverting amplifier closed-loop gain Av to maintain steady-state oscillation?

• Af0 ≈ 1.59 kHz, Av = 3.0
• Bf0 ≈ 3.18 kHz, Av = 1.0
• Cf0 ≈ 1.59 kHz, Av = 10.0
• Df0 ≈ 10.0 kHz, Av = 2.0

A standard 555 timer is configured in astable multivibrator mode with timing resistors RA = 4.7 kΩ and RB = 10.0 kΩ, and capacitor C = 100 nF. What is the approximate oscillation frequency f and the duty cycle D (percentage of period when output is HIGH)?

• Af ≈ 584 Hz, D ≈ 59.5%
• Bf ≈ 405 Hz, D ≈ 59.5%
• Cf ≈ 584 Hz, D ≈ 40.5%
• Df ≈ 980 Hz, D ≈ 59.5%

A step-down (buck) DC-DC switching converter operates in continuous conduction mode (CCM) with an input voltage Vin = 24.0 V, an output voltage Vout = 5.0 V, a switching frequency fs = 200 kHz, and an inductor L = 47 μH. Assuming ideal components, what is the operating duty cycle D and the peak-to-peak inductor ripple current Delta_IL?

• AD ≈ 0.208 (20.8%), ΔIL ≈ 0.421 A
• BD ≈ 0.208 (20.8%), ΔIL ≈ 2.02 A
• CD ≈ 0.792 (79.2%), ΔIL ≈ 0.421 A
• DD ≈ 0.208 (20.8%), ΔIL ≈ 0.532 A

A step-up (boost) DC-DC switching regulator is required to convert an unregulated input voltage Vin = 12.0 V to a regulated output voltage Vout = 36.0 V in continuous conduction mode. Assuming ideal components, what is the required switch duty cycle D?

• A0.67 (66.7%)
• B0.33 (33.3%)
• C0.75 (75.0%)
• D0.50 (50.0%)

A linear voltage regulator (such as an LM7805) supplies a regulated 5.0 V rail to an embedded microcontroller system drawing a continuous load current of Iload = 800 mA from a 12.0 V DC power supply. If the regulator quiescent current is Iq = 10 mA, what is the total power dissipated as heat in the regulator package, and what is its electrical power efficiency?

• APdiss ≈ 5.72 W, efficiency ≈ 41.2%
• BPdiss ≈ 4.00 W, efficiency ≈ 50.0%
• CPdiss ≈ 9.60 W, efficiency ≈ 25.0%
• DPdiss ≈ 1.20 W, efficiency ≈ 80.5%

A digital circuit specification requires minimizing the Boolean function F(A,B,C,D) = Σm(0, 2, 8, 10, 14, 15) using a Karnaugh map. Which of the following represents the minimal Sum of Products (SOP) expression?

• AF = B'D' + ACD
• BF = B'D' + ABC
• CF = A'B'D' + ACD
• DF = B'C'D' + ABC + ABD

An engineer needs to implement the three-variable Boolean function F(X, Y, Z) = Σm(1, 2, 4, 7) using an 8-to-1 multiplexer with active-HIGH enable. If select inputs S2, S1, S0 are connected to variables X, Y, Z respectively, what logic levels must be tied to data inputs I0 through I7?

• AI1=I2=I4=I7 = 1; I0=I3=I5=I6 = 0
• BI1=I2=I4=I7 = 0; I0=I3=I5=I6 = 1
• CI0=I1=I2=I3 = 1; I4=I5=I6=I7 = 0
• DI0=I2=I4=I6 = 1; I1=I3=I5=I7 = 0

A combinational logic circuit realizes the function F = A'B + AC. When B = 1 and C = 1, and input A transitions from 1 to 0, an unwanted transient glitch (momentary pulse to 0) is observed at output F. What type of hazard is this, and how is it eliminated?

• AStatic-1 hazard; eliminated by adding the consensus term BC to form F = A'B + AC + BC
• BStatic-0 hazard; eliminated by inverting the output stage
• CDynamic hazard; eliminated by inserting an RC delay in the B input path
• DEssential hazard; eliminated by switching from Mealy to Moore architecture

A power transistor dissipates P = 10 W and must keep its junction below TJmax = 150 °C in an enclosure at TA = 40 °C. The datasheet gives θJC = 1.5 °C/W, and the insulating thermal pad adds θCS = 0.5 °C/W. What is the maximum sink-to-ambient thermal resistance θSA of the heat sink to be purchased?

• A9.0 °C/W
• B11.0 °C/W
• C10.5 °C/W
• D13.0 °C/W

In an electrostatic-discharge protected area (EPA) for assembling electronic boards, why does a grounded wrist strap include a series resistor of about 1 MΩ?

• ATo limit current through the operator if the strap touches an energized conductor, while…
• BTo raise the operator's body voltage so that components are not damaged by charge from th…
• CTo act as a fuse that opens the ground connection when an electrostatic discharge occurs
• DTo filter 60 Hz noise from the operator's body so that measurements on the board are more…

A 4-bit synchronous binary up-counter is constructed using four positive edge-triggered JK flip-flops (Q0, Q1, Q2, Q3, with Q0 being the LSB). Which input excitation equations correctly configure flip-flops JK1, JK2, and JK3?

• AJ1=K1 = Q0; J2=K2 = Q0*Q1; J3=K3 = Q0*Q1*Q2
• BJ1=K1 = 1; J2=K2 = Q1; J3=K3 = Q2
• CJ1=K1 = Q0'; J2=K2 = Q1'; J3=K3 = Q2'
• DJ1=K1 = Q0+Q1; J2=K2 = Q1+Q2; J3=K3 = Q2+Q3

In VHDL hardware description language, what is the fundamental purpose of the process sensitivity list, and how does the synthesis tool interpret a combinational process if a signal read inside the process is omitted from the sensitivity list?

• AThe sensitivity list specifies which signal events trigger the process in simulation; syn…
• BThe sensitivity list defines the clock domain frequency for synthesis; omitting a signal…
• CThe sensitivity list contains only the reset signals; omitting a signal converts the circ…
• DThe sensitivity list dictates output pin assignments on the FPGA; omitting a signal groun…

In Verilog HDL, what is the standard recommended practice regarding the use of blocking (=) versus non-blocking (<=) procedural assignments?

• AUse non-blocking assignments (<=) for modeling sequential logic registers, and blocking a…
• BUse blocking assignments (=) for modeling sequential logic registers, and non-blocking as…
• CUse non-blocking assignments (<=) exclusively across all always blocks regardless of circ…
• DUse blocking assignments (=) exclusively in edge-triggered always blocks to avoid race co…

In an ARM Cortex-M microcontroller architecture, what is the role of the Nested Vectored Interrupt Controller (NVIC) regarding interrupt preemption?

• AIt allows a higher-priority interrupt to immediately preempt an actively executing lower-…
• BIt converts all hardware interrupts into software polling loops executed in the backgroun…
• CIt prevents any interrupt from nesting, guaranteeing that every ISR completes before anot…
• DIt dynamically alters CPU core clock frequency to match the arrival rate of peripheral re…

A microcontroller hardware timer peripheral is clocked from a system bus frequency fsys = 48.0 MHz. The timer has a 16-bit prescaler register and a 16-bit auto-reload register (ARR). To generate an exact periodic interrupt at f_int = 1.0 kHz with a prescaler value PSC = 47 (which divides the clock by PSC + 1 = 48), what value must be loaded into the auto-reload register ARR?

• A999
• B1000
• C4800
• D47999

In surface-mount (SMT) assembly of a new electronic board, what is the correct order of the main process steps?

• ASolder paste printing through a stencil → component placement (pick and place) → reflow s…
• BComponent placement → solder paste printing → wave soldering → reflow soldering
• CReflow soldering of the bare board → solder paste printing → component placement → inspec…
• DAutomated optical inspection → component placement → solder paste printing → reflow solde…

Why is a solderless breadboard a poor choice for prototyping a 20 MHz oscillator or a converter that switches several amperes?

• AIts long contact strips add stray capacitance (a few pF between rows) and inductance, and…
• BIt cannot hold through-hole components with standard 2.54 mm (0.1 in) lead spacing
• CIt short-circuits all components placed in the same row across the central channel
• DIt only accepts digital integrated circuits and cannot hold passive components

The Inter-Integrated Circuit (I2C) serial bus uses open-drain/open-collector output drivers on both SDA and SCL lines. Why are external pull-up resistors required, and what mechanism enables bus arbitration between multiple masters?

• APull-up resistors passively restore lines to logic HIGH; wired-AND logic allows a master…
• BPull-up resistors set the differential impedance to 120 Ω; token ring passing prevents mu…
• CPull-up resistors eliminate electromagnetic radiation; arbitration is performed by a dedi…
• DPull-up resistors act as anti-aliasing filters; collisions are detected using CSMA/CD bac…

In a Controller Area Network (CAN 2.0B) physical bus, what differential voltage state defines a dominant bit, and which logical binary value does a dominant bit represent during identifier arbitration?

• AVdiff ≈ 2.0 V (CAN_H ≈ 3.5 V, CAN_L ≈ 1.5 V); represents logical 0 and wins arbitration.
• BVdiff ≈ 0.0 V (CAN_H ≈ 2.5 V, CAN_L ≈ 2.5 V); represents logical 1 and wins arbitration.
• CVdiff ≈ 5.0 V (CAN_H ≈ 5.0 V, CAN_L ≈ 0.0 V); represents logical 1 and loses arbitration.
• DVdiff ≈ -2.0 V (CAN_H ≈ 1.5 V, CAN_L ≈ 3.5 V); represents logical 0 and loses arbitration.

A standard amplitude modulated (AM) transmitter broadcasts with an unmodulated carrier power Pc = 1000 W. If the carrier is sinusoidally modulated with a modulation index m = 0.80 (80%), what is the total transmitted power Pt and what portion of power is contained in the two sidebands?

• APt = 1320 W; sideband power = 320 W
• BPt = 1640 W; sideband power = 640 W
• CPt = 1800 W; sideband power = 800 W
• DPt = 1160 W; sideband power = 160 W

A commercial FM broadcasting signal has a peak frequency deviation Delta_f = 75.0 kHz and a maximum modulating audio frequency fm = 15.0 kHz. According to Carson's bandwidth rule, what is the approximate transmission bandwidth B required for this signal?

• A180 kHz
• B150 kHz
• C90 kHz
• D165 kHz

In digital modulation schemes, how many bits of information are transmitted per modulation symbol in 16-QAM (Quadrature Amplitude Modulation) and 64-QAM constellations?

• A4 bits/symbol for 16-QAM, and 6 bits/symbol for 64-QAM
• B2 bits/symbol for 16-QAM, and 4 bits/symbol for 64-QAM
• C8 bits/symbol for 16-QAM, and 16 bits/symbol for 64-QAM
• D16 bits/symbol for 16-QAM, and 64 bits/symbol for 64-QAM

A lossless transmission line with characteristic impedance Z0 = 50.0 Ω is terminated in a resistive load ZL = 150.0 Ω. What are the voltage reflection coefficient Gamma and the Voltage Standing Wave Ratio (VSWR)?

• AGamma = +0.50, VSWR = 3.0
• BGamma = -0.50, VSWR = 0.33
• CGamma = +0.67, VSWR = 5.0
• DGamma = +0.50, VSWR = 2.0

A radio frequency engineer must match a 50.0 Ω transmission line to a 200.0 Ω resistive antenna feedpoint at 1.0 GHz using a quarter-wave (lambda/4) transformer. What characteristic impedance Z_match must the quarter-wave line section have?

• A100.0 Ω
• B125.0 Ω
• C75.0 Ω
• D150.0 Ω

What is the physical resonant length of a half-wave center-fed dipole antenna designed for an operating frequency f = 300 MHz in free space (speed of light c ≈ 3.0 * 10^8 m/s), and what is its nominal theoretical radiation resistance at resonance?

• ALength = 0.50 m, radiation resistance ≈ 73 Ω
• BLength = 1.00 m, radiation resistance ≈ 50 Ω
• CLength = 0.25 m, radiation resistance ≈ 36.5 Ω
• DLength = 2.00 m, radiation resistance ≈ 300 Ω

The older IPC-2221 design charts allow an internal PCB conductor only about half the current of an external conductor of the same cross-section for the same temperature rise. What assumption underlies this derating?

• AInternal traces are surrounded by epoxy-glass dielectric (FR-4) which has low thermal con…
• BInternal traces experience higher skin effect losses at DC than surface traces.
• CInternal copper foils have higher bulk electrical resistivity than electrodeposited exter…
• DInternal traces are subjected to hydrostatic pressure during lamination, which thins the…

In high-speed PCB layout, how does increasing the width (w) of a surface microstrip trace affect its characteristic impedance Z0, assuming substrate dielectric constant (epsilon_r) and height above the ground plane (h) remain constant?

• ACharacteristic impedance Z0 decreases because capacitance per unit length increases and i…
• BCharacteristic impedance Z0 increases because cross-sectional copper resistance decreases.
• CCharacteristic impedance Z0 remains strictly constant because Z0 depends solely on the su…
• DCharacteristic impedance Z0 increases linearly because wider traces capture more magnetic…

A high-speed CMOS digital microcontroller causes a dynamic transient current step Delta_I = 500 mA during clock edge switching over a duration Delta_t = 2.0 ns. If the power distribution network (PDN) allows a maximum power rail voltage droop Delta_V = 50 mV, what is the minimum decoupling capacitance C required directly adjacent to the IC power pins?

• A20 nF
• B2.0 nF
• C200 nF
• D5.0 nF

Why do high-frequency electronic systems utilize surface-mount ceramic capacitors (such as MLCCs in 0402 or 0603 packages) for IC power rail decoupling rather than through-hole electrolytic capacitors?

• ASMD ceramic capacitors exhibit dramatically lower Equivalent Series Inductance (ESL) and…
• BSMD ceramic capacitors have higher capacitance density per unit volume at frequencies bel…
• CThrough-hole electrolytic capacitors cannot handle DC bias voltages above 3.3 V.
• DElectrolytic capacitors act as short circuits to DC voltages due to chemical polarization.

What undesirable electromagnetic phenomenon occurs when a high-speed digital signal trace is routed directly across a split or slot in its reference ground plane on a multi-layer printed circuit board?

• AThe high-frequency return current cannot flow directly beneath the trace, creating a larg…
• BThe signal trace becomes an open circuit due to capacitive decoupling.
• CThe dielectric constant of the laminate drops to zero across the split.
• DThe DC supply current is diverted entirely into the digital ground pins of adjacent ICs.

In mixed-signal PCB design involving sensitive analog circuits and noisy digital microcontrollers, what is the purpose of implementing a star ground (or single-point connection) between analog ground (AGND) and digital ground (DGND)?

• ATo prevent high-amplitude, high-frequency digital return currents and ground bounce from…
• BTo step down the ground voltage by half across the analog subsystem.
• CTo provide galvanic isolation equivalent to an optical isolator between the domains.
• DTo eliminate the need for analog low-pass filtering and shielding.

In electromagnetic compatibility (EMC) testing, what is the distinction between differential-mode and common-mode conducted noise on a power cable, and which component is specifically designed to suppress common-mode noise?

• ADifferential-mode noise flows in opposite directions on line and neutral conductors; comm…
• BDifferential-mode noise flows in the same direction on all conductors; common-mode noise…
• CDifferential-mode noise is strictly radiated; common-mode noise is strictly electrostatic…
• DDifferential-mode noise occurs only at DC; common-mode noise occurs only at AC; suppresse…

What is skin depth (delta) in a metallic copper conductor, and how does it scale as the operating frequency f of an alternating current signal increases?

• ASkin depth is the depth at which current density drops to 1/e (≈ 37%) of its surface valu…
• BSkin depth is the thickness of the solder mask; it increases linearly with signal frequen…
• CSkin depth is the penetration depth of electrostatic fields; it is directly proportional…
• DSkin depth is the dielectric thickness between layers; it remains constant across all fre…

When a high-speed differential signal pair transitions from a top signal layer to an internal layer through PCB vias, why is it critical to place ground return stitching vias immediately adjacent to the signal vias?

• ATo provide a low-inductance, continuous return current path between reference planes, pre…
• BTo increase the DC resistance of the ground plane around the signal via.
• CTo dissipate heat generated by dielectric losses directly to the chassis.
• DTo act as a low-frequency decoupling capacitor between layers.

During reflow soldering of small two-terminal surface-mount components (such as 0402 or 0603 chip resistors and capacitors), what manufacturing defect known as 'tombstoning' occurs, and what PCB pad design technique mitigates it?

• AThe component stands on end due to unbalanced solder surface tension forces; mitigated by…
• BThe component cracks due to electrostatic discharge; mitigated by conformal coating.
• CThe component sinks into the laminate due to excessive solder paste; mitigated by solder…
• DThe component shifts horizontally into adjacent pads; mitigated by increasing stencil thi…

In modern high-density PCB layouts utilizing fine-pitch Ball Grid Array (BGA) components with pitch <= 0.8 mm, what routing strategy is commonly employed to escape inner balls without violating trace width and clearance rules?

• ADog-bone fanout with via-in-pad or laser microvias on High Density Interconnect (HDI) bui…
• BSingle-layer surface routing using 20-mil wide copper traces
• CManual through-hole jumper wire soldering on the secondary side
• DStar topology routing exclusively on the bottom solder layer

Under the standard IPC-A-610 (Acceptability of Electronic Assemblies), which product class designates electronics where continuous performance or performance-on-demand is critical, equipment downtime cannot be tolerated, and the equipment must function in extreme environments (such as medical life-support or aerospace systems)?

• AClass 3 (High Performance / Harsh Environment Electronic Products)
• BClass 1 (General Electronic Products)
• CClass 2 (Dedicated Service Electronic Products)
• DClass 4 (Consumer Entertainment Products)

According to IPC-A-610 solder joint visual inspection criteria, what contact wetting angle (theta) between the solder fillet and the copper land is indicative of acceptable, proper intermetallic metallurgical bonding?

• AA wetting angle theta <= 90° forming a smooth concave meniscus fillet
• BA wetting angle theta >= 120° forming a spherical ball over the pad
• CA wetting angle of exactly 180° with zero pad adhesion
• DA wetting angle between 95° and 135° showing convex surface contour