CENEVAL EGEL Plus Ingeniería Computacional (EGEL Plus ICOMPU)

A microprocessor memory subsystem has an L1 cache hit time of 1 ns with an L1 miss rate of 5%. The L2 cache has a hit time of 4 ns with a local miss rate of 20%. The main memory access penalty is 50 ns. What is the Average Memory Access Time (AMAT) of this system?

• A1.70 ns
• B3.70 ns
• C1.20 ns
• D11.20 ns

A system uses 32-bit byte-addressed physical memory and a 256 KB 8-way set-associative cache with 64-byte blocks. How are the 32 address bits divided into Tag, Index, and Block Offset fields?

• ATag: 17 bits, Index: 9 bits, Offset: 6 bits
• BTag: 14 bits, Index: 12 bits, Offset: 6 bits
• CTag: 16 bits, Index: 10 bits, Offset: 6 bits
• DTag: 18 bits, Index: 8 bits, Offset: 6 bits

A synchronous digital pipeline stage consists of edge-triggered D flip-flops with clock-to-Q delay t_cq = 0.8 ns, setup time t_setup = 1.0 ns, and hold time t_hold = 0.5 ns. The critical combinational logic path delay between flip-flops is 6.2 ns with a clock skew of 0.0 ns. What is the theoretical maximum clock frequency (f_max) for reliable operation?

• A125.0 MHz
• B142.9 MHz
• C161.3 MHz
• D117.6 MHz

An embedded microcontroller operates with a system clock of 16 MHz. An engineer configures an internal 16-bit up-counting timer with a prescaler of 8 to generate a periodic PWM carrier frequency of exactly 1.0 kHz in fast PWM mode (counting from 0 to TOP). What value must be loaded into the TOP register?

• A1999
• B2000
• C15999
• D999

A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) uses an analog reference voltage of Vref = 3.30 V with an input range from 0 V to Vref. What is the ideal quantization step size (voltage resolution of 1 LSB) of this converter?

• A3.22 mV
• B6.45 mV
• C1.61 mV
• D0.32 mV

Which minimal sum-of-products (SOP) boolean expression represents the output F(A,B,C,D) defined by minterms Σm(0, 2, 8, 10) in a 4-variable Karnaugh map?

• AB' D'
• BA' C'
• CB' C
• DA D'

In synchronous sequential circuit design, which condition MUST hold to prevent a hold time violation at the destination flip-flop?

• At_cq_min + t_comb_min ≥ t_hold + t_skew
• Bt_cq_max + t_comb_max + t_setup ≤ T_clock
• Ct_comb_max ≥ t_cq_max + t_setup
• Dt_skew ≥ t_hold - t_cq_min

What phenomenon occurs in an unclocked or level-sensitive JK latch when both inputs J and K are held HIGH (J = 1, K = 1) while the enable/clock pulse remains active longer than the propagation delay of the gates?

• ARace-around condition causing uncontrollable toggling of the output
• BMetastability causing the output voltage to lock at the midpoint logic threshold
• CPermanent gate burnout due to internal bus contention
• DImmediate latch reset to Q = 0 regardless of prior state

What is the primary architectural difference between a Moore finite state machine (FSM) and a Mealy finite state machine?

• AMoore outputs depend solely on the current state, whereas Mealy outputs depend on both cu…
• BMoore machines require fewer states than Mealy machines to implement any arbitrary sequen…
• CMealy machines update state registers asynchronously, whereas Moore machines require a sy…
• DMoore machines evaluate outputs purely during clock transitions, whereas Mealy machines c…

An 8-to-1 digital multiplexer has three selection lines S2, S1, S0 connected to inputs A, B, and C respectively. To implement the boolean function F(A, B, C, D) = A'B'C'D + A'BC'D' + ABC, what signals must be applied to data inputs I0 through I7?

• AI0 = D, I2 = D', I7 = 1, with all other inputs tied to 0
• BI0 = D, I2 = D', I6 = 1, I7 = 1, with all other inputs tied to 0
• CI1 = D, I3 = D', I7 = 1, with all other inputs tied to 0
• DI0 = D', I2 = D, I7 = 1, with all other inputs tied to 0

In a classical 5-stage RISC instruction pipeline (IF, ID, EX, MEM, WB), which hazard type CANNOT be completely eliminated by hardware forwarding (bypassing) alone and requires inserting at least one stall cycle (bubble)?

• ALoad-use data hazard where an instruction immediately uses the result of a preceding LOAD…
• BALU-to-ALU data hazard where an ADD instruction uses the result of an immediately precedi…
• CStructural hazard on the register file write port during concurrent execution
• DBranch penalty when the branch outcome is resolved in the ID stage with branch target pre…

A 2-bit saturating counter branch predictor is currently in the 'Weakly Taken' state (10 in binary). The branch instruction is executed and is evaluated as 'Not Taken'. What is the new state of the 2-bit counter?

• AWeakly Not Taken (01)
• BStrongly Not Taken (00)
• CStrongly Taken (11)
• DRemains in Weakly Taken (10)

What is the key difference between a write-through cache policy and a write-back cache policy in computer architecture?

• AWrite-through updates both cache and main memory simultaneously on every write, whereas w…
• BWrite-through writes directly to main memory bypassing the cache completely, whereas writ…
• CWrite-back requires an immediate bus transaction on every write hit, whereas write-throug…
• DWrite-through utilizes a dirty bit per cache line to track modified data, whereas write-b…

Which set of architectural characteristics is representative of a pure Reduced Instruction Set Computer (RISC) architecture such as ARM or MIPS, compared to a CISC architecture like x86?

• AFixed-length instructions, load/store architecture, large general-purpose register file,…
• BVariable-length instructions, memory-to-memory arithmetic operations, microcode engine, a…
• CDirect execution of high-level language statements in silicon, specialized complex instru…
• DAbsence of pipelining, non-orthogonal instruction set, and heavy reliance on microcoded m…

In computer system buses, what is the primary operational distinction between a synchronous bus and an asynchronous bus?

• AA synchronous bus coordinates all bus transfers relative to a common shared clock signal,…
• BA synchronous bus transmits data serially over a single wire, whereas an asynchronous bus…
• CAn asynchronous bus can only support a single master, whereas a synchronous bus allows mu…
• DA synchronous bus has variable transaction timing based on device response speed, whereas…

When a hardware interrupt request (IRQ) is accepted by a microcontroller's Nested Vectored Interrupt Controller (NVIC), what sequence of actions is automatically performed before the first instruction of the Interrupt Service Routine (ISR) executes?

• AThe current processor context (including PC and PSR) is pushed to the stack, the vector t…
• BThe program counter is reset to 0x00000000, all peripheral clocks are gated off, and the…
• COnly the program counter is saved in a dedicated register; the ISR must save every other…
• DThe main program must first poll the interrupt flag, save the registers manually, and the…

In the I2C (Inter-Integrated Circuit) serial communication protocol, how does a bus master signal a START condition on the physical bus?

• ATransitioning the SDA line from HIGH to LOW while the SCL line remains HIGH
• BTransitioning the SCL line from HIGH to LOW while the SDA line remains HIGH
• CHolding both SDA and SCL LOW simultaneously for at least 10 clock periods
• DSending nine consecutive HIGH pulses on the SCL line with SDA held LOW

A microcontroller communicates with an external flash memory using Serial Peripheral Interface (SPI) Mode 3. What are the defined clock polarity (CPOL) and clock phase (CPHA) settings for Mode 3?

• ACPOL = 1 (idle HIGH), CPHA = 1 (data sampled on trailing/rising edge)
• BCPOL = 0 (idle LOW), CPHA = 0 (data sampled on leading/rising edge)
• CCPOL = 1 (idle HIGH), CPHA = 0 (data sampled on leading/falling edge)
• DCPOL = 0 (idle LOW), CPHA = 1 (data sampled on trailing/falling edge)

During asynchronous serial UART reception (8-N-1 configuration), the receiver detects that the stop bit line state is logic LOW instead of the expected logic HIGH at the anticipated stop bit sampling time. Which hardware error flag will the UART controller raise?

• AFraming Error (FE)
• BParity Error (PE)
• COverrun Error (OE)
• DBreak Detection (BD)

What is the primary operational advantage of utilizing a Direct Memory Access (DMA) controller for high-throughput peripheral transfers (such as Ethernet or ADC buffers) in an embedded system?

• AIt transfers blocks of data directly between peripherals and RAM without requiring CPU co…
• BIt doubles the physical bandwidth of the DDR SDRAM chips by overclocking the memory contr…
• CIt gives each peripheral a private memory so the CPU and peripherals never share the syst…
• DIt executes the interrupt service routine in hardware so that the CPU never has to handle…

When measuring temperature in an industrial process using a Pt100 Resistance Temperature Detector (RTD) located 50 meters away from the measurement instrumentation, why is a 4-wire Kelvin connection preferred over a 2-wire connection?

• AIt completely cancels measurement errors caused by lead wire resistance and lead resistan…
• BIt allows the RTD to be powered with alternating current (AC) without requiring an analog…
• CIt amplifies the Pt100 signal from millivolts directly up to a standard 4-20 mA current l…
• DIt prevents electrostatic magnetic coupling by grounding both ends of the platinum sensor…

In what standard cyclical sequence does a Programmable Logic Controller (PLC) execute its repetitive operating cycle?

• AInput scan (read physical inputs into image table) → Program execution (ladder logic eval…
• BOutput scan → Program execution → Input scan → Compilation to native machine code
• CHousekeeping → Immediate asynchronous interrupt dispatch → Input scan → Power cycle check
• DProgram execution → Clock synchronization → Input polling → Flash EEPROM rewrite

In PLC ladder logic motor control, why is software and hardware interlocking implemented between the Forward and Reverse contactor control rungs?

• ATo prevent both forward and reverse contactors from energizing simultaneously, which woul…
• BTo increase the rotational starting torque of the induction motor by pulsing both winding…
• CTo ensure that the thermal overload relay resets automatically after every operating cycle
• DTo synchronize the PLC internal processor clock with the 60 Hz industrial AC mains freque…

What is the primary technical advantage of a Solid-State Relay (SSR) featuring zero-crossing detection over an electromechanical relay (EMR) when switching AC resistive heater loads?

• AVery long switching life with no contact wear, silent operation, and low switching noise…
• BZero forward voltage drop across the semiconductor junction, generating zero heat dissipa…
• CComplete electrical galvanic isolation without requiring optocouplers or magnetic transfo…
• DAbility to conduct DC current in both directions without polarity restrictions

In a closed-loop Proportional-Integral-Derivative (PID) controller, what is the primary role of the Derivative (D) control action?

• AIt anticipates future error based on the rate of change of the error signal, providing da…
• BIt eliminates residual steady-state error by accumulating error over elapsed time
• CIt provides immediate control effort proportional to the instantaneous magnitude of the c…
• DIt filters out high-frequency noise from sensor feedback lines before it reaches the actu…

An enterprise network engineer is allocated the block 192.168.10.0/24 and needs to create a subnet for a department requiring a minimum of 28 usable host IP addresses. Which subnet mask minimizes address waste while satisfying this requirement?

• A255.255.255.224 (/27)
• B255.255.255.240 (/28)
• C255.255.255.192 (/26)
• D255.255.255.248 (/29)

A host interface is assigned the IPv4 address 172.16.45.142 with a subnet mask of 255.255.240.0 (/20). What are the network address and directed broadcast address of this subnet?

• ANetwork: 172.16.32.0, Broadcast: 172.16.47.255
• BNetwork: 172.16.40.0, Broadcast: 172.16.47.255
• CNetwork: 172.16.45.0, Broadcast: 172.16.45.255
• DNetwork: 172.16.32.0, Broadcast: 172.16.63.255

A 1.0 Gbps (1 × 10⁹ bps) transatlantic fiber connection has a Round-Trip Time (RTT) of 80 milliseconds. What is the Bandwidth-Delay Product (BDP) in bytes, representing the minimum TCP window size required to saturate the channel?

• A10,000,000 bytes (10.0 MB)
• B80,000,000 bytes (80.0 MB)
• C1,250,000 bytes (1.25 MB)
• D65,535 bytes (64 KB)

A data packet of 1,500 bytes (12,000 bits) is transmitted over a 10 Mbps point-to-point link of length 2,000 km. The propagation speed of electromagnetic signals in the fiber medium is 2.0 × 10⁸ m/s. What are the transmission delay (t_trans) and propagation delay (t_prop) for this packet?

• ATransmission delay = 1.20 ms, Propagation delay = 10.00 ms
• BTransmission delay = 10.00 ms, Propagation delay = 1.20 ms
• CTransmission delay = 0.15 ms, Propagation delay = 1.00 ms
• DTransmission delay = 1.20 ms, Propagation delay = 100.00 ms

How many total usable host IPv4 addresses can be assigned to endpoint interfaces in a classless /22 network block?

• A1,022
• B1,024
• C2,046
• D510

At which layer of the OSI 7-layer reference model does an IP router make path determination decisions based on destination logical addresses, and what is the Protocol Data Unit (PDU) at this layer?

• ALayer 3 (Network Layer) — Packet
• BLayer 2 (Data Link Layer) — Frame
• CLayer 4 (Transport Layer) — Segment
• DLayer 1 (Physical Layer) — Bit

What is the exact sequence of control flags exchanged during the standard TCP three-way handshake to establish a reliable bidirectional transport connection between a client and a server?

• AClient sends SYN → Server responds with SYN-ACK → Client sends ACK
• BClient sends ACK → Server responds with SYN → Client sends SYN-ACK
• CClient sends SYN → Server responds with ACK → Server sends SYN-ACK
• DClient sends FIN → Server responds with ACK → Server sends FIN-ACK

How does TCP implement flow control between an endpoint transmitter and an endpoint receiver?

• AThe receiver advertises its available buffer capacity in the 16-bit Window field of ackno…
• BThe sender periodically pings the receiver's default gateway with ICMP Source Quench mess…
• CThe receiver dynamically adjusts the sender's IP Time to Live (TTL) hop count to force pa…
• DThe intermediate routers dynamically modify the TCP Checksum field to signal buffer satur…

A network host uses Stateless Address Autoconfiguration (SLAAC) with the modified EUI-64 format to generate an interface ID from its 48-bit MAC address: 00:1A:2B:3C:4D:5E. What is the resulting 64-bit interface identifier?

• A021A:2BFF:FE3C:4D5E
• B001A:2BFF:FE3C:4D5E
• C021A:2BFE:FF3C:4D5E
• D001A:2BEE:EE3C:4D5E

Which reserved prefix designates an IPv6 Link-Local unicast address, and what is its defined routability scope?

• Afe80::/10 — valid and routable only on the local physical link; never forwarded across a…
• Bfc00::/7 — routable across global internet backbones without NAT
• C2001::/16 — reserved for multicast rendezvous point discovery across enterprise intranets
• Dff02::/16 — routable across multiple autonomous systems for anycast services

An Ethernet switch receives a frame on port Gi0/2 with source MAC address 0011.2233.4455 and destination MAC address AABB.CCDD.EEFF. What does the switch do if the destination MAC address is NOT found in its Content Addressable Memory (CAM) table?

• ARecords source MAC 0011.2233.4455 mapped to port Gi0/2 in the CAM table and floods the fr…
• BDrops the frame immediately and sends an ICMP Host Unreachable message to port Gi0/2
• CBroadcasts an ARP request to determine which host owns MAC AABB.CCDD.EEFF
• DForwards the frame exclusively to the configured default gateway port

In IEEE 802.1Q VLAN trunking, where is the 4-byte 802.1Q tag inserted within the standard Ethernet frame, and how many bits are allocated to identify the VLAN ID (VID)?

• ABetween the Source MAC address and EtherType/Length fields; 12 bits allocated to the VLAN…
• BAt the very beginning of the Preamble; 16 bits allocated to the VLAN ID (VID)
• CImmediately after the Payload data before the Frame Check Sequence (FCS); 8 bits allocate…
• DInside the IP Header Options field; 10 bits allocated to the VLAN ID (VID)

In a local area network running the IEEE 802.1D Spanning Tree Protocol (STP), what criteria determine which switch is elected as the Root Bridge?

• AThe switch with the lowest Bridge ID (BID), evaluated first by lowest Bridge Priority and…
• BThe switch with the highest Bridge ID (BID), determined by highest IP address
• CThe switch with the largest number of physically connected active Gigabit Ethernet ports
• DThe switch that has been continuously powered on for the longest duration (highest uptime)

What is the operational state of a non-designated switch port in IEEE 802.1D Spanning Tree Protocol that discards user data frames, does not populate its MAC address table, but continuously receives BPDUs to monitor network topology changes?

• ABlocking state
• BListening state
• CLearning state
• DForwarding state

How does Dynamic ARP Inspection (DAI) prevent ARP poisoning (spoofing) attacks on an enterprise access switch?

• AIt intercepts ARP packets on untrusted switchports and validates IP-to-MAC bindings again…
• BIt encrypts all ARP broadcast requests using 256-bit AES before transmitting them across…
• CIt completely disables all Address Resolution Protocol broadcasts, requiring all endpoint…
• DIt resets the TCP connection of any host whose MAC address transmits more than 10 ARP fra…

Which mathematical algorithm does Open Shortest Path First (OSPF) execute to compute its loop-free shortest path tree, and what is its default path metric inversely proportional to?

• ADijkstra algorithm; metric is Cost, inversely proportional to interface bandwidth (Refere…
• BBellman-Ford algorithm; metric is Hop Count, inversely proportional to physical cable len…
• CFloyd-Warshall algorithm; metric is Administrative Distance, inversely proportional to li…
• DKruskal algorithm; metric is Delay, inversely proportional to MTU packet size

In a broadcast multi-access Ethernet network segment running OSPF, why are a Designated Router (DR) and Backup Designated Router (BDR) elected, and what multicast address do non-DR routers use to send Link-State Updates to them?

• ATo reduce full-mesh adjacencies from n(n-1)/2 to 2n; non-DR routers send updates to 224.0…
• BTo provide default gateway redundancy for end-user PCs; non-DR routers send updates to 22…
• CTo encrypt OSPF packets using Kerberos tickets; non-DR routers send updates to 224.0.0.9…
• DTo negotiate MTU sizes dynamically; non-DR routers send updates to 224.0.0.10 (EIGRP)

Which mechanism in distance-vector routing protocols prevents routing loops by prohibiting a router from advertising a routing update back out of the same physical interface on which it was originally learned?

• ASplit Horizon
• BPoison Reverse
• CHold-down Timer
• DRoute Summarization

How does the Border Gateway Protocol (BGP-4) detect and prevent routing loops across different Autonomous Systems (AS)?

• AIt inspects the AS_PATH attribute; if a router receives an UPDATE containing its own loca…
• BIt calculates a 32-bit CRC checksum across all exterior gateway router interfaces every 3…
• CIt restricts exterior routing to a maximum diameter of 15 autonomous hops
• DIt forces all BGP speakers to connect to a central global root route reflector located at…

A 12 V DC source feeds a voltage divider made of R1 = 6 kΩ (in series) and R2 = 3 kΩ (from the output node to ground). What is the Thévenin equivalent seen from the output node to ground?

• AV_th = 4 V, R_th = 2 kΩ
• BV_th = 8 V, R_th = 2 kΩ
• CV_th = 4 V, R_th = 9 kΩ
• DV_th = 12 V, R_th = 3 kΩ

What is the correct 4-step message sequence and transport protocol used when an IPv4 host acquires network configuration parameters from a DHCP server?

• ADHCPDISCOVER → DHCPOFFER → DHCPREQUEST → DHCPACK, over UDP ports 67 (server) and 68 (clie…
• BDHCPREQUEST → DHCPOFFER → DHCPDISCOVER → DHCPACK, over TCP port 80
• CDHCPINIT → DHCPOFFER → DHCPCONFIRM → DHCPACK, over UDP ports 53 and 54
• DDHCPOFFER → DHCPDISCOVER → DHCPACK → DHCPREQUEST, over ICMP protocol 1

In the Domain Name System (DNS), which resource record type maps an alias domain name to its canonical domain name, and which record type maps a domain name directly to a 128-bit IPv6 address?

• ACNAME record maps an alias to a canonical name; AAAA record maps to an IPv6 address
• BPTR record maps an alias to a canonical name; A record maps to an IPv6 address
• CMX record maps an alias to a canonical name; NS record maps to an IPv6 address
• DSOA record maps an alias to a canonical name; TXT record maps to an IPv6 address