CPN CPE — Computer Engineering (CEN) Track (Nigeria)

Which of the following represents the minimized Boolean expression for the function F(A, B, C, D) = Σm(0, 2, 5, 7, 8, 10, 13, 15) using a Karnaugh map?

• AB'D' + BD
• BA'B' + CD
• CAD' + B'C
• DAC' + BD'

What is the primary difference between a Mealy machine and a Moore machine in sequential logic design?

• AA Mealy machine's outputs depend on both the current state and the current inputs, wherea…
• BA Moore machine's outputs depend on both the current state and the current inputs, wherea…
• CA Mealy machine is always asynchronous, whereas a Moore machine is synchronous.
• DA Moore machine requires fewer states than a Mealy machine to implement the same sequence…

In VLSI design, what physical phenomenon is primarily responsible for the 'latch-up' condition in CMOS circuits?

• AThe activation of parasitic bipolar junction transistors (BJTs) forming a silicon-control…
• BThe breakdown of the gate oxide due to excessive electrostatic discharge (ESD).
• CThe electromigration of metal atoms in the interconnect layers under high current densiti…
• DThe injection of hot carriers into the oxide, causing a permanent shift in threshold volt…

What is the critical path in a synchronous digital circuit, and how does it restrict the circuit's operation?

• AIt is the longest propagation delay path between any two registers, and it determines the…
• BIt is the path with the shortest propagation delay, and it determines the hold time requi…
• CIt is the power distribution line that carries the highest current, limiting thermal diss…
• DIt is the clock distribution tree path, limiting the maximum skew across the chip.

Which type of hazard can occur in combinational logic circuits due to unequal propagation delays along different paths, and how is it resolved?

• AStatic hazards, which are resolved by adding redundant prime implicants to the logic expr…
• BDynamic hazards, which are resolved by increasing the system clock frequency.
• CStructural hazards, which are resolved by duplicating ALU resources.
• DData hazards, which are resolved by adding pipeline registers.

What is the purpose of inserting scan chains in a digital integrated circuit design during the testing phase?

• ATo convert sequential flip-flops into shift registers to improve the observability and co…
• BTo increase the speed of the global clock distribution network.
• CTo monitor power consumption across different segments of the die in real time.
• DTo automatically bypass manufacturing defects by rerouting critical signals.

Which of the following defines the 'setup time' (t_setup) of a edge-triggered D flip-flop?

• AThe minimum time that the D input data must remain stable before the active clock edge.
• BThe minimum time that the D input data must remain stable after the active clock edge.
• CThe time required for the Q output to reach 50% of its final state after the clock transi…
• DThe duration of the clock pulse required to ensure internal latching.

In CMOS technology, why is the PMOS transistor typically designed to be wider than the NMOS transistor in a standard logic inverter?

• AHoles have lower mobility than electrons, so a wider PMOS is needed to balance the rise a…
• BPMOS transistors operate at higher temperatures, requiring larger channel areas for heat…
• CThe threshold voltage of PMOS is naturally lower, which must be compensated by a wider ga…
• DWider PMOS gates reduce the parasitic input capacitance of the inverter.

Which of the following logic families exhibits the absolute lowest static power dissipation?

• ACMOS (Complementary Metal-Oxide-Semiconductor)
• BTTL (Transistor-Transistor Logic)
• CECL (Emitter-Coupled Logic)
• DBiCMOS (Bipolar CMOS)

What is the primary function of a multiplexer in combinational logic design?

• ATo select one of many inputs and route it to a single output based on control signals.
• BTo decode a binary input into a one-hot active output line.
• CTo store data temporarily based on a clock pulse.
• DTo perform arithmetic operations such as addition and subtraction.

What does metastability mean in a sequential digital circuit, and how is it commonly mitigated?

• AA state where a register output hovers between 0 and 1 before settling, mitigated by casc…
• BA condition where the logic gates melt due to thermal runaway, mitigated by passive cooli…
• CAn impedance mismatch on a transmission line, mitigated by termination resistors.
• DA state where the clock frequency drifts from its target, mitigated by a Phase-Locked Loo…

Which of the following blocks is a combinational logic circuit that performs the addition of three input bits (two significant bits and a carry-in) to produce a sum and a carry-out?

• AFull Adder
• BHalf Adder
• CDecoder
• DPriority Encoder

What is the function of a Look-Ahead Carry Generator in arithmetic hardware systems?

• ATo compute carry bits in parallel using generate and propagate terms, reducing the propag…
• BTo predict the branch direction in high-speed instruction pipelines.
• CTo buffer data outputs in sequential registers to avoid clock race conditions.
• DTo convert serial data streams into parallel buses.

Which fault model is most commonly used in digital logic testing to represent a physical defect that causes a signal line to be permanently tied to log-level high or low?

• AStuck-at fault model (Stuck-at-0 / Stuck-at-1)
• BBridging fault model
• CPath delay fault model
• DTransient fault model

What is the logic function of a standard 2-input NAND gate when one of its inputs is tied permanently to a logic 1?

• AAn inverter (NOT gate)
• BA buffer (YES gate)
• CAn AND gate
• DAn OR gate

Which of the following sequential elements is level-sensitive rather than edge-triggered?

• ALatch
• BFlip-flop
• CCounter
• DShift register

Which theorem states that any logic function can be implemented using only NAND gates or only NOR gates?

• AFunctional Completeness (Universal Logic)
• BDe Morgan's Theorem
• CShannon's Expansion Theorem
• DBoolean Duality Theorem

In sequential timing analysis, what is 'clock skew'?

• AThe spatial difference in arrival times of the clock signal at different flip-flops.
• BThe variation in the clock period over time (jitter).
• CThe delay added by clock buffers to balance path lengths.
• DThe signal attenuation along clock transmission lines.

Which of the following registers is used to convert serial data inputs into parallel data outputs?

• ASIPO (Serial-In Parallel-Out) Shift Register
• BPISO (Parallel-In Serial-Out) Shift Register
• CSISO (Serial-In Serial-Out) Shift Register
• DPIPO (Parallel-In Parallel-Out) Shift Register

What is the primary benefit of dynamic logic circuits compared to static CMOS circuits?

• ALower input capacitance and faster switching speeds.
• BZero static and dynamic power consumption.
• CHigh noise immunity and tolerance to voltage fluctuations.
• DSimple design verification requiring no clock signal.

How does a Von Neumann computer architecture differ from a Harvard computer architecture?

• AVon Neumann architecture uses a unified memory bus for both instructions and data, wherea…
• BHarvard architecture uses a unified memory bus for both instructions and data, whereas Vo…
• CVon Neumann architectures are strictly RISC, while Harvard architectures are CISC.
• DHarvard architectures store instructions in non-volatile ROM while data is stored in vola…

In a pipelined processor, which hazard occurs when a instruction requires data that has not yet been computed by a preceding instruction?

• AData hazard
• BControl hazard
• CStructural hazard
• DBranch hazard

A 4-way set-associative cache has a total capacity of 64 KB, with a block size of 64 bytes. If the physical address space is 32 bits, how many bits are allocated for the Index and Tag fields respectively?

• AIndex: 8 bits, Tag: 18 bits
• BIndex: 10 bits, Tag: 16 bits
• CIndex: 12 bits, Tag: 14 bits
• DIndex: 6 bits, Tag: 20 bits

What is the function of the Program Counter (PC) in a CPU?

• ATo hold the memory address of the next instruction to be fetched and executed.
• BTo decode the current instruction and generate control signals.
• CTo count the number of instructions executed since system boot.
• DTo store intermediate arithmetic results from the ALU.

Which of the following describes the 'write-through' policy in cache design?

• AData is written to both the cache block and the main memory block simultaneously.
• BData is written only to the cache, and main memory is updated later when the block is evi…
• CData bypasses the cache entirely and is written directly to main memory.
• DData is written to cache only when there is a cache miss.

In the 8086 microprocessor architecture, how is a 20-bit physical memory address generated from 16-bit registers?

• ABy shifting the Segment Register left by 4 bits and adding the Offset Register.
• BBy shifting the Segment Register right by 4 bits and adding the Offset Register.
• CBy concatenating the Segment Register and the Offset Register directly.
• DBy adding the Segment Register and the Offset Register directly.

What is the purpose of the Translation Lookaside Buffer (TLB) in virtual memory systems?

• ATo cache recent virtual-to-physical address translations, speeding up memory accesses.
• BTo act as a temporary storage area for instructions fetched out-of-order.
• CTo convert digital signals into analog signals for peripheral interfaces.
• DTo manage page evictions from main memory to hard disk space.

Which of the following CPU techniques allows instructions to execute simultaneously in multiple parallel execution units within a single processor core?

• ASuperscalar execution
• BPipelining
• CMultithreading
• DMicroprogramming

What is the primary feature of Direct Memory Access (DMA) in computer interfacing?

• AIt allows external I/O devices to transfer data directly to or from main memory without i…
• BIt enables the CPU to access the cache memory directly without going through the bus cont…
• CIt provides direct, unencrypted internet connectivity to embedded devices.
• DIt connects the ALU directly to the register file to bypass control logic.

Which of the following registers in a processor stores the results of comparison instructions and contains bits indicating zero, carry, sign, and overflow conditions?

• AStatus Register (Flags Register)
• BInstruction Register (IR)
• CAccumulator
• DStack Pointer (SP)

What is 'interrupt latency' in microprocessors?

• AThe time interval between the generation of an interrupt signal and the execution of the…
• BThe duration of the execution of the Interrupt Service Routine (ISR).
• CThe time required to fetch the interrupt vector from memory.
• DThe delay caused by disabling interrupts during critical sections.

In a RISC processor architecture, what is the primary purpose of having a large register file?

• ATo minimize slow memory access operations by keeping operand variables in registers.
• BTo allow the CPU to decode multiple complex instructions simultaneously.
• CTo store microprogrammed instructions for CISC emulation.
• DTo increase the speed of the virtual memory page table translation.

Which of the following protocols is a synchronous serial communication interface that uses four wires (MISO, MOSI, SCK, CS)?

• ASPI (Serial Peripheral Interface)
• BI2C (Inter-Integrated Circuit)
• CUART (Universal Asynchronous Receiver-Transmitter)
• DRS-232

What is the function of a watchdog timer in microcontroller-based embedded systems?

• ATo reset the microcontroller if the software gets stuck in an infinite loop or crashes.
• BTo count clock cycles for precise pulse-width modulation (PWM) output.
• CTo measure the battery voltage level and trigger low-power standby modes.
• DTo synchronize external peripherals using a common clock reference.

Which addressing mode specifies the operand value directly within the instruction itself, rather than referring to a register or memory location?

• AImmediate addressing mode
• BDirect addressing mode
• CRegister indirect addressing mode
• DIndex addressing mode

What is the primary purpose of a cache coherency protocol in a multi-core processor system?

• ATo ensure that all cores see the same data value when reading a shared memory location.
• BTo maximize the transfer rate of the main memory bus.
• CTo prevent pipeline stalls caused by data dependency hazards.
• DTo allocate cache lines dynamically based on thread priority.

In computer architecture, what does the term 'instruction pipelining' refer to?

• AOverlapping the execution stages of multiple instructions to increase instruction through…
• BGrouping multiple registers into a single array to speed up operations.
• CRouting instruction streams through a dedicated serial communications port.
• DExecuting multiple threads concurrently on a single core.

Which interrupt line in the Intel 8086 microprocessor has the highest priority and cannot be masked by software?

• ANMI (Non-Maskable Interrupt)
• BINTR (Interrupt Request)
• CTRAP
• DRESET

What is the role of the Memory Management Unit (MMU) in a computer system?

• ATo translate virtual addresses used by software into physical addresses in RAM, and enfor…
• BTo physically route data signals between the CPU and the memory modules on the motherboar…
• CTo store data blocks temporarily to bridge speed differences between the CPU and memory.
• DTo perform garbage collection and deallocate memory blocks in the background.

In a CPU, what is the 'control store' used for?

• ATo store the microcode sequence that defines the instruction set of a microprogrammed pro…
• BTo cache memory address tags for quick lookup during L1 cache accesses.
• CTo buffer incoming interrupts before they are processed by the priority encoder.
• DTo store the configuration settings of the motherboard BIOS.

What is the primary difference between SRAM (Static RAM) and DRAM (Dynamic RAM)?

• ASRAM stores data in bistable latch circuits (usually 6 transistors) and does not require…
• BDRAM stores data in bistable latch circuits (usually 6 transistors) and does not require…
• CSRAM is non-volatile, while DRAM is volatile.
• DDRAM is faster and more expensive than SRAM, making it suitable for L1 caches.

Which of the following terms describes the mismatch in processor speed and memory access time, where a CPU must wait idle for data to load from RAM?

• AMemory Wall
• BVon Neumann bottleneck
• CPipelining stall
• DBus contention

What is the purpose of the accumulator register in early microprocessor architectures?

• ATo store one of the input operands and the output result of arithmetic and logic operatio…
• BTo store the memory address of the next instruction to be fetched.
• CTo hold the offset address for segment calculations.
• DTo act as a buffer for serial I/O communication.

Which of the following statements is true regarding RISC-V?

• AIt is an open-standard Instruction Set Architecture (ISA) based on established RISC desig…
• BIt is a proprietary architecture owned by Intel for high-performance servers.
• CIt requires a microcode control store to translate instructions.
• DIt is a single-board computer used for educational embedded projects.

What is the primary advantage of Using a Harvard architecture in digital signal processors (DSPs)?

• AIt allows simultaneous fetching of instructions and data, enabling high-speed mathematica…
• BIt reduces the total number of pins on the processor package.
• CIt simplifies the compiler design by using a unified memory model.
• DIt eliminates the need for cache memory entirely.

In real-time operating systems (RTOS) designed for embedded computer systems, what is 'priority inversion'?

• AA situation where a low-priority task holds a shared resource needed by a high-priority t…
• BA software bug where the priority levels of all tasks are accidentally reversed in memory.
• CA scheduling policy that alternates execution between the highest and lowest priority tas…
• DAn electrical fault where the interrupt priority register bits are inverted.